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公开(公告)号：US11082035B1
公开(公告)日：2021-08-03
申请号：US17030160
申请日：2020-09-23
摘要： A digitally controlled delay line (DCDL) includes an input terminal, an output terminal, and a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal. Each stage of the plurality of stages includes first and second inverters configured to selectively propagate the signal along the first signal path, third and fourth inverters configured to selectively propagate the signal along the second signal path, and a fifth inverter configured to selectively propagate the signal from the first signal path to the second signal path.
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公开(公告)号：US10170414B2
公开(公告)日：2019-01-01
申请号：US15693083
申请日：2017-08-31
发明人： Chia-Hsin Hu , Yu-Chiun Lin , Yi-Hsuan Chung , Chung-Peng Hsieh , Chung-Chieh Yang , Po-Nien Chen
IPC分类号： H01L23/522 , H01L49/02 , H01L27/11582
摘要： A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
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公开(公告)号：US10161967B2
公开(公告)日：2018-12-25
申请号：US14991936
申请日：2016-01-09
IPC分类号： G01R19/00 , G01R13/00 , G01R31/28 , G01R13/02 , G01R31/317
摘要： A device is disclosed that includes a control circuit, a scope circuit and a time-to-current converter. The control circuit configured to delay a voltage signal for a delay time to generate a first control signal, and to generate a second control signal according to the first control signal and the voltage signal. The scope circuit configured to generate a first current signal in response to the second control signal and the voltage signal. The time-to-current converter configured to generate a second current signal according to the first control signal and the voltage signal.
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公开(公告)号：US20160071806A1
公开(公告)日：2016-03-10
申请号：US14944907
申请日：2015-11-18
发明人： Jaw-Juinn Horng , Chung-Peng Hsieh
IPC分类号： H01L23/552 , H01L23/528 , H01L23/538
CPC分类号： H01L23/552 , H01L23/481 , H01L23/528 , H01L23/5384 , H01L23/5386 , H01L23/585 , H01L25/0657 , H01L2225/06513 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.
摘要翻译： 在一些实施例中，集成电路器件包括半导体衬底。 有源区设置在半导体衬底中。 第一保护环设置在半导体衬底中并且完全围绕有源区域。 第一保护环具有第一导电类型。 A通孔穿过半导体衬底并且与有源区间隔开，使得通孔设置在第一保护环的外部。 第二保护环设置在半导体衬底中，并且整个包围通孔和第一保护环。 第二保护环具有第一导电类型并且与第一保护环不相交。
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公开(公告)号：US11835551B2
公开(公告)日：2023-12-05
申请号：US18069813
申请日：2022-12-21
IPC分类号： G01R19/00 , G01R13/00 , G01R13/02 , G01R31/28 , G01R31/317
CPC分类号： G01R13/00 , G01R13/0218 , G01R31/2851 , G01R31/31726
摘要： A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.
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公开(公告)号：US11574104B2
公开(公告)日：2023-02-07
申请号：US17135565
申请日：2020-12-28
发明人： Chung-Ting Lu , Chih-Chiang Chang , Chung-Peng Hsieh , Chung-Chieh Yang , Yung-Chow Peng , Yung-Shun Chen , Tai-Yi Chen , Nai Chen Cheng
IPC分类号： G06F30/392 , G06F30/36 , G06F30/367 , G06F30/394
摘要： An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.
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公开(公告)号：US10823765B2
公开(公告)日：2020-11-03
申请号：US15965994
申请日：2018-04-30
发明人： Yung-Chow Peng , Chung-Peng Hsieh
摘要： A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.
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公开(公告)号：US20190277891A1
公开(公告)日：2019-09-12
申请号：US15965994
申请日：2018-04-30
发明人： Yung-Chow Peng , Chung-Peng Hsieh
摘要： A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.
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公开(公告)号：US12033937B2
公开(公告)日：2024-07-09
申请号：US17099002
申请日：2020-11-16
发明人： Chia-Hsin Hu , Yu-Chiun Lin , Yi-Hsuan Chung , Chung-Peng Hsieh , Chung-Chieh Yang , Po-Nien Chen
IPC分类号： H01L23/522 , H01L49/02 , H10B43/27
CPC分类号： H01L23/5228 , H01L28/00 , H01L28/24 , H10B43/27
摘要： A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.
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公开(公告)号：US10510637B2
公开(公告)日：2019-12-17
申请号：US15883462
申请日：2018-01-30
发明人： Chung-Chieh Yang , Yung-Chow Peng , Chung-Peng Hsieh , Sa-Lly Liu
IPC分类号： H01L29/00 , H01L23/34 , H01L23/64 , H01L23/552 , H01L23/522 , H01L49/02
摘要： A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.
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