公开(公告)号：US12033937B2

公开(公告)日：2024-07-09

申请号：US17099002

申请日：2020-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02 ,  H10B43/27

CPC classification number: H01L23/5228 ,  H01L28/00 ,  H01L28/24 ,  H10B43/27

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US11056396B1

公开(公告)日：2021-07-06

申请号：US16728154

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wu ,  Ming-Hung Han ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

公开(公告)号：US20210057286A1

公开(公告)日：2021-02-25

申请号：US16547942

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhen Geng ,  Kitchun Kwong ,  Taicheng Shieh ,  Bo-Shiuan Shie ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.

公开(公告)号：US10707315B2

公开(公告)日：2020-07-07

申请号：US16390515

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Henry Kwong ,  Chih-Yung Lin ,  Po-Nien Chen ,  Chen Hua Tsai

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US10312334B2

公开(公告)日：2019-06-04

申请号：US15141951

申请日：2016-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Henry Kwong ,  Chih-Yung Lin ,  Po-Nien Chen ,  Chen Hua Tsai

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US09773731B2

公开(公告)日：2017-09-26

申请号：US15009500

申请日：2016-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsin Hu ,  Yu-Chiun Lin ,  Yi-Hsuan Chung ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Po-Nien Chen

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/24

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

公开(公告)号：US20210375697A1

公开(公告)日：2021-12-02

申请号：US17404443

申请日：2021-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hui Hsu ,  Po-Nien Chen ,  Yi-Hsuan Chung ,  Bo-Shiuan Shie ,  Chih-Yung Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

公开(公告)号：US11127639B2

公开(公告)日：2021-09-21

申请号：US16547942

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhen Geng ,  Kitchun Kwong ,  Taicheng Shieh ,  Bo-Shiuan Shie ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.

公开(公告)号：US10700160B2

公开(公告)日：2020-06-30

申请号：US16512315

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chiun Lin ,  Po-Nien Chen ,  Chen Hua Tsai ,  Chih-Yung Lin

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L23/522 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US11024703B2

公开(公告)日：2021-06-01

申请号：US16914528

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chiun Lin ,  Po-Nien Chen ,  Chen Hua Tsai ,  Chih-Yung Lin

IPC: H01L23/522 ,  H01L29/66 ,  H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.