公开(公告)号：US11681854B2

公开(公告)日：2023-06-20

申请号：US17703898

申请日：2022-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367 ,  G06F30/3953 ,  G06F30/373 ,  G06F119/06

CPC classification number: G06F30/398 ,  G06F30/367 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/373 ,  G06F2119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

公开(公告)号：US12073167B2

公开(公告)日：2024-08-27

申请号：US18163916

申请日：2023-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

公开(公告)号：US11670672B2

公开(公告)日：2023-06-06

申请号：US17306796

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

公开(公告)号：US20200227516A1

公开(公告)日：2020-07-16

申请号：US16834265

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

IPC: H01L49/02 ,  H01L23/522

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

公开(公告)号：US12032896B2

公开(公告)日：2024-07-09

申请号：US18312835

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/3953 ,  G06F119/06

CPC classification number: G06F30/398 ,  G06F30/367 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/373 ,  G06F2119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.

公开(公告)号：US11574104B2

公开(公告)日：2023-02-07

申请号：US17135565

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

公开(公告)号：US10998397B2

公开(公告)日：2021-05-04

申请号：US16834265

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

IPC: H01L49/02 ,  H01L23/522

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

公开(公告)号：US11308255B2

公开(公告)日：2022-04-19

申请号：US16886550

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chieh Yang ,  Tai-Yi Chen ,  Yun-Ru Chen ,  Yung-Chow Peng

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367 ,  G06F30/3953 ,  G06F30/373 ,  G06F119/06

Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.