知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.047 seconds)

    SEMICONDUCTOR DEVICE AND METHOD
    2.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD 审中-公开

    公开(公告)号：US20230261052A1

    公开(公告)日：2023-08-17

    申请号：US17650712

    申请日：2022-02-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Yu Lin ,  Ming-Hua Yu ,  Yee-Chia Yeo

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L29/0847 ,  H01L29/66795 ,  H01L29/045 ,  H01L21/0262 ,  H01L29/785 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02609

    Abstract: A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

    FINFET Device and Method of Forming Same
    4.
    发明申请
    FINFET Device and Method of Forming Same 有权

    公开(公告)号：US20220302282A1

    公开(公告)日：2022-09-22

    申请号：US17805581

    申请日：2022-06-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Wei Lee ,  Che-Yu Lin ,  Hsueh-Chang Sung ,  Yee-Chia Yeo

    IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/67 ,  H01L29/08 ,  H01L29/04 ,  H01J37/32 ,  H01L29/78 ,  H01L21/762

    Abstract: A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

    SOURCE AND DRAIN EPITAXY RE-SHAPING
    10.
    发明申请
    SOURCE AND DRAIN EPITAXY RE-SHAPING 审中-公开

    公开(公告)号：US20180366373A1

    公开(公告)日：2018-12-20

    申请号：US15625501

    申请日：2017-06-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kun-Mu LI ,  Chih-Chiang Chang ,  Wen-Chu Hsiao ,  Che-Yu Lin ,  Wei-Siang Yang

    IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78

    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

Patent Agency Ranking