公开(公告)号：US12237404B2

公开(公告)日：2025-02-25

申请号：US18336328

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Lin ,  Chien-Hung Chen ,  Wen-Chu Hsiao

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L29/08 ,  H01L29/165 ,  H01L29/40 ,  H01L29/78

Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

公开(公告)号：US10297690B2

公开(公告)日：2019-05-21

申请号：US15725091

申请日：2017-10-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Liang-Yi Chen ,  Wen-Chu Hsiao

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

公开(公告)号：US10269648B1

公开(公告)日：2019-04-23

申请号：US15857381

申请日：2017-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Chih-Chiang Chang ,  Wen-Chu Hsiao

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.

公开(公告)号：US10727131B2

公开(公告)日：2020-07-28

申请号：US15625501

申请日：2017-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Chih-Chiang Chang ,  Wen-Chu Hsiao ,  Che-Yu Lin ,  Wei-Siang Yang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L21/3065 ,  H01L29/78

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

公开(公告)号：US20230343858A1

公开(公告)日：2023-10-26

申请号：US18336328

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Lin ,  Chien-Hung Chen ,  Wen-Chu Hsiao

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/30 ,  H01L29/40 ,  H01L29/08 ,  H01L21/762 ,  H01L29/165 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/3003 ,  H01L29/401 ,  H01L29/0847 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/7833 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/31116 ,  H01L29/66545 ,  H01L29/7851 ,  H01L21/02381 ,  H01L29/66636 ,  H01L21/26513

Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

公开(公告)号：US11527442B2

公开(公告)日：2022-12-13

申请号：US17169090

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Lin ,  Chien-Wei Lee ,  Chien-Hung Chen ,  Wen-Chu Hsiao ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

公开(公告)号：US20180366373A1

公开(公告)日：2018-12-20

申请号：US15625501

申请日：2017-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu LI ,  Chih-Chiang Chang ,  Wen-Chu Hsiao ,  Che-Yu Lin ,  Wei-Siang Yang

IPC: H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

公开(公告)号：US20210159122A1

公开(公告)日：2021-05-27

申请号：US17169090

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Lin ,  Chien-Wei Lee ,  Chien-Hung Chen ,  Wen-Chu Hsiao ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

公开(公告)号：US09698263B2

公开(公告)日：2017-07-04

申请号：US14945542

申请日：2015-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lai-Wan Chong ,  Wen-Chu Hsiao ,  Ying-Min Chou ,  Hsiang-Hsiang Ko

IPC: H01L29/04 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.

公开(公告)号：US11309418B2

公开(公告)日：2022-04-19

申请号：US16417051

申请日：2019-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Liang-Yi Chen ,  Wen-Chu Hsiao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/768 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.