Invention Application
- Patent Title: SOURCE/DRAIN FORMATION WITH REDUCED SELECTIVE LOSS DEFECTS
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Application No.: US18789176Application Date: 2024-07-30
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Publication No.: US20240387702A1Publication Date: 2024-11-21
- Inventor: Chih-Chiang Chang , Ming-Hua Yu , Li-Li Su
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/20 ; H01L21/8234 ; H01L27/092 ; H01L29/417 ; H01L29/78

Abstract:
A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.
Information query
IPC分类: