公开(公告)号：US20220336643A1

公开(公告)日：2022-10-20

申请号：US17847448

申请日：2022-06-23

Applicant: Tessera LLC

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/22 ,  H01L21/225 ,  H01L21/311 ,  H01L21/324 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/768 ,  H01L29/417 ,  H01L21/762

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

公开(公告)号：US11615988B2

公开(公告)日：2023-03-28

申请号：US17482903

申请日：2021-09-23

Applicant: Tessera LLC

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L21/306 ,  H01L21/324

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

公开(公告)号：US20220344211A1

公开(公告)日：2022-10-27

申请号：US17750953

申请日：2022-05-23

Applicant: TESSERA LLC

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78

Abstract: An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

公开(公告)号：US20240038594A1

公开(公告)日：2024-02-01

申请号：US18115302

申请日：2023-02-28

Applicant: TESSERA LLC

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L29/0649 ,  H01L29/785 ,  H01L29/41791 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/6653

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.