公开(公告)号：US12075615B2

公开(公告)日：2024-08-27

申请号：US17205563

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Suhwan Lim ,  Hyeyoung Kwon

IPC: H01L27/11556 ,  G11C5/06 ,  H01L23/538 ,  H01L27/11582 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.

公开(公告)号：US12035521B2

公开(公告)日：2024-07-09

申请号：US17205563

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Suhwan Lim ,  Hyeyoung Kwon

IPC: H01L27/11556 ,  G11C5/06 ,  H01L23/538 ,  H01L27/11582 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.

公开(公告)号：US12193235B2

公开(公告)日：2025-01-07

申请号：US17537984

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek Oh ,  Hyeyoung Kwon ,  Taein Kim ,  Gukhyon Yon ,  Minhyun Lee

IPC: H10B43/27

Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.