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公开(公告)号：US11903197B2
公开(公告)日：2024-02-13
申请号：US17148334
申请日：2021-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suhwan Lim , Jaehun Jung , Sanghoon Kim , Taehun Kim , Seongchan Lee
Abstract: A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode.
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公开(公告)号：US11621855B2
公开(公告)日：2023-04-04
申请号：US17062949
申请日：2020-10-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sunghyuk Lee , Sooyeon Kim , Juyoung Kim , Jaehun Jung , Jinki Jung
Abstract: An electronic device that performs a digital signature for a blockchain address and first information associated with the blockchain address using a private key, associates and stores signature data obtained as a result of performing the digital signature with at least one of the blockchain address or the first information, performs authentication for the blockchain address and the first information using a public key corresponding to the private key, based on the stored signature data, and displays the blockchain address and the first information, based on the result of performing the authentication is provided.
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Patent Agency Ranking
公开(公告)号：US09786675B2
公开(公告)日：2017-10-10
申请号：US15043640
申请日：2016-02-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehun Jung , Zhiliang Xia , Daewoong Kang , Dae Sin Kim , Kwang Soo Seol , Homin Son , Seunghyun Lim
IPC: H01L29/788 , H01L27/11568 , H01L29/423 , H01L29/792
CPC classification number: H01L27/11568 , H01L27/1157 , H01L27/11582 , H01L29/4234 , H01L29/42364 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/792 , H01L29/7923
Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.
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公开(公告)号：US12035521B2
公开(公告)日：2024-07-09
申请号：US17205563
申请日：2021-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehun Jung , Suhwan Lim , Hyeyoung Kwon
IPC: H01L27/11556 , G11C5/06 , H01L23/538 , H01L27/11582 , H10B41/27 , H10B43/27
CPC classification number: H10B41/27 , G11C5/06 , H01L23/5386 , H10B43/27
Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.
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公开(公告)号：US12213316B2
公开(公告)日：2025-01-28
申请号：US17720376
申请日：2022-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suhwan Lim , Nambin Kim , Samki Kim , Taehun Kim , Hanvit Yang , Changhee Lee , Jaehun Jung , Hyeongwon Choi
Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.
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公开(公告)号：US12075615B2
公开(公告)日：2024-08-27
申请号：US17205563
申请日：2021-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehun Jung , Suhwan Lim , Hyeyoung Kwon
IPC: H01L27/11556 , G11C5/06 , H01L23/538 , H01L27/11582 , H10B41/27 , H10B43/27
CPC classification number: H10B41/27 , G11C5/06 , H01L23/5386 , H10B43/27
Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.
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公开(公告)号：US11114747B2
公开(公告)日：2021-09-07
申请号：US16441376
申请日：2019-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chungkyun Ham , Seunggil Jeon , Jaehun Jung , Youngsik Kim
Abstract: An electronic device is provided. The electronic device includes a housing including a first plate, a second plate facing away from the first plate, and a side member surrounding a space between the first plate and the second plate, a first PCB disposed in parallel with the first plate in the space between the first plate and the second plate, and including a first face facing the first plate and a second face facing the second plate, at least one conductive plate formed on the second face, a first conductive pattern embedded in the first PCB and disposed to be closer to a portion of the side member than the conductive plate when viewed from above the first plate, a first wireless communication circuit mounted on a first face of the first PCB, electrically coupled to the conductive plate and the first conductive pattern.
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