公开(公告)号：US11639550B2

公开(公告)日：2023-05-02

申请号：US17501146

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Gu Kim ,  Homin Son ,  Junghyeon Kim ,  Hangkyu Song ,  Eunha Oh ,  Oleg Feygenson ,  Donghyun Jang ,  Sung-Woo Jeon ,  Wooyeon Hwang

IPC: H01L21/67 ,  C23C16/46 ,  H01L21/02 ,  C23C16/455 ,  C23C16/448 ,  C23C16/458

Abstract: An apparatus for depositing a thin layer and associated method, the apparatus including a process chamber; a support in the process chamber, substrates being supportable on the support at different heights; a gas injector configured to inject a gas into the process chamber; and a heater configured to heat the process chamber, wherein the gas injector includes a first injector configured to inject a first gas; and a second injector configured to inject a second gas, a flow rate of the first gas injected from the first injector ranges from 120 sccm to 240 sccm, and a flow rate of the second gas injected from the second injector ranges from 1,200 sccm to 2,400 sccm.

公开(公告)号：US09786675B2

公开(公告)日：2017-10-10

申请号：US15043640

申请日：2016-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Zhiliang Xia ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L29/788 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7923

Abstract: A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes. An energy band gap of the first charge storage layer is smaller than those of the second and third charge storage layers. The first charge storage layer is thicker than the second and third charge storage layers.

公开(公告)号：US09831265B2

公开(公告)日：2017-11-28

申请号：US15165135

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nambin Kim ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Changsub Lee ,  Seunghyun Lim ,  Sunghoi Hur

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: Provided is a semiconductor device including a substrate, gate electrodes vertically stacked on the substrate, insulating patterns between the gate electrodes, an active pillar provided to penetrate the gate electrodes and the insulating patterns and electrically coupled with the substrate, and a memory pattern provided between the gate electrodes and the active pillar and between the insulating patterns and the active pillar. The gate electrodes include edge portions extending between the memory pattern and the insulating patterns.

公开(公告)号：US12230514B2

公开(公告)日：2025-02-18

申请号：US17499988

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byunghwan Kong ,  Heeyeon Kim ,  Homin Son ,  Geunkyu Choi

IPC: H01L21/67

Abstract: A substrate processing method includes: disposing a wafer in a wafer region of a tube; injecting an inert gas into a gap region, of the tube, between an inner side wall of the tube and the wafer disposed in the wafer region; and injecting a process gas into the wafer region of the tube, wherein a pressure of the gap region of the tube is higher than a pressure at an edge of the wafer region of the tube during the injection of the inert gas and the process gas.

公开(公告)号：US09741735B2

公开(公告)日：2017-08-22

申请号：US14993485

申请日：2016-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Wook Lee ,  Daewoong Kang ,  Dae Sin Kim ,  Kwang Soo Seol ,  Homin Son ,  Seunghyun Lim

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/42348

Abstract: A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating patterns, an active pillar passing through the stack and electrically connected to the substrate and a charge storing layer interposed between the stack and the active pillar. The charge storing layer includes a first portion between the active pillar and one of the gate patterns, a second portion between the active pillar and one of the insulating patterns, and a third portion joining the first portion to the second portion and having a thickness less than that of the first portion.