公开(公告)号：US12213316B2

公开(公告)日：2025-01-28

申请号：US17720376

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan Lim ,  Nambin Kim ,  Samki Kim ,  Taehun Kim ,  Hanvit Yang ,  Changhee Lee ,  Jaehun Jung ,  Hyeongwon Choi

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US20240413079A1

公开(公告)日：2024-12-12

申请号：US18629785

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Samki Kim ,  Nambin Kim ,  Taehun Kim

IPC: H01L23/528 ,  H01L25/065 ,  H01L29/78 ,  H10B41/27 ,  H10B43/27 ,  H10B80/00

Abstract: The present disclosure relates to semiconductor devices, in which a semiconductor device includes: a plate layer, gate electrodes stacked and spaced apart from each other on the plate layer in a first direction, the gate electrodes including first gate electrodes and second gate electrodes on the first gate electrodes; a horizontal insulating layer between the first gate electrodes and the second gate electrode; first channel structures extending through the first gate electrodes in the first direction; second channel structures extending through the second gate electrodes in the first direction and electrically connected to the first channel structures, respectively; contact plugs extending through the horizontal insulating layer in the first direction and connected to the gate electrodes, respectively; dummy vertical structures extending through the horizontal insulating layer in the first direction and around the contact plugs, and a cell region insulating layer covering upper surfaces of the dummy vertical structures.