Semiconductor memory device
    1.
    发明授权

    公开(公告)号:US12185533B2

    公开(公告)日:2024-12-31

    申请号:US18351096

    申请日:2023-07-12

    Inventor: Hideto Takekida

    Abstract: According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

    Semiconductor device
    2.
    发明授权

    公开(公告)号:US12068053B2

    公开(公告)日:2024-08-20

    申请号:US17903889

    申请日:2022-09-06

    Inventor: Hideto Takekida

    CPC classification number: G11C5/06 G11C16/08

    Abstract: A semiconductor device includes a substrate, a first external connection pad separated from the substrate in a first direction, which is a thickness direction thereof, a first coil separated from the substrate in the first direction and electrically connected to the connection pad, a first stacked body between the connection pad and the substrate and between the first coil and the substrate, the first stacked body including a first insulator, a first wiring therein, and a first pad electrically connected to the wiring, and a second stacked body between the first stacked body and the substrate, the second stacked body including a second insulator, a second wiring therein, a second pad electrically connected to the second wiring, and a second coil. The first insulator contacts the second insulator. The first pad contacts the second pad. A part of the first coil overlaps the second coil in the first direction.

    Semiconductor device and method of manufacturing the same

    公开(公告)号:US11502100B2

    公开(公告)日:2022-11-15

    申请号:US17011451

    申请日:2020-09-03

    Abstract: According to one embodiment, the stacked body includes a first stacked portion including a plurality of electrode layers, a second stacked portion including a plurality of electrode layers, and being disposed separately from the first stacked portion in the first direction, and a connection portion including a high dielectric layer provided between the first stacked portion and the second stacked portion and having a dielectric constant higher than a dielectric constant of the insulator. The column-shaped portion includes a first portion provided in the first stacked portion and extending in the first direction of the stacked body, a second portion provided in the second stacked portion and extending in the first direction, and an intermediate portion provided in the connection portion and connected the first portion to the second portion.

    Semiconductor storage device
    5.
    发明授权

    公开(公告)号:US11869851B2

    公开(公告)日:2024-01-09

    申请号:US17189725

    申请日:2021-03-02

    Inventor: Hideto Takekida

    Abstract: A semiconductor storage device includes a substrate, a first stacked body provided above the substrate and having a side portion configured in a staircase pattern, a plurality of columnar portions passing through the first stacked body, a second stacked body provided in an outer edge portion of the substrate, and a plurality of first slits. The first stacked body include a plurality of first insulating layers and a plurality of conductive layers that are alternately stacked. The second stacked body includes the plurality of first insulating layers and the plurality of conductive layers that are alternately stacked. The plurality of first slits extends through the first and second stacked bodies in a direction intersecting a stacking direction of the first stacked body.

    Semiconductor storage device
    7.
    发明授权

    公开(公告)号:US11386959B2

    公开(公告)日:2022-07-12

    申请号:US17191563

    申请日:2021-03-03

    Inventor: Hideto Takekida

    Abstract: A semiconductor storage device includes a memory string and a row decoder configured to apply voltages to first to fourth select gate lines and first and second word lines connected to the memory string. A sequencer has first mode for erasing the entire memory string and a second mode for erasing just a portion of the memory string. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines.

    Semiconductor storage device with insulating layers for etching stop

    公开(公告)号:US11887926B2

    公开(公告)日:2024-01-30

    申请号:US17188423

    申请日:2021-03-01

    CPC classification number: H01L23/5226 H10B41/27 H10B43/10 H10B43/27 H10B43/40

    Abstract: A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.

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