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    System and Method Providing Run-Time Parallelization of Computer Software Accommodating Data Dependencies
    3.
    发明申请
    System and Method Providing Run-Time Parallelization of Computer Software Accommodating Data Dependencies 有权
    提供计算机软件运行时并行化的系统和方法，适应数据依赖

    公开(公告)号：US20120047353A1

    公开(公告)日：2012-02-23

    申请号：US12858907

    申请日：2010-08-18

    申请人： Gagan Gupta ,  Gurindar S. Schi ,  Srinath Sridharan

    发明人： Gagan Gupta ,  Gurindar S. Schi ,  Srinath Sridharan

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3838 ,  G06F8/314 ,  G06F8/456 ,  G06F8/458 ,  G06F9/4881 ,  G06F9/5033 ,  G06F9/5038

    摘要： A system and method of parallelizing programs employs runtime instructions to identify data accessed by program portions and to assign those program portions to particular processors based on potential overlap between the access data. Data dependence between different program portions may be identified and used to look for pending “predicate” program portions that could create data dependencies and to postpone program portions that may be dependent while permitting parallel execution of other program portions.

    摘要翻译： 并行程序的系统和方法采用运行时指令来识别由程序部分访问的数据，并且基于访问数据之间的潜在重叠将这些程序部分分配给特定的处理器。 可以识别不同程序部分之间的数据依赖性，并用于查找可能创建数据依赖性的待定“预定”程序部分，并推迟可能依赖于同时允许其他程序部分的并行执行的程序部分。

    System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens
    7.
    发明申请
    System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens 有权
    使用数据关联令牌提供计算机软件的运行时并行化的系统和方法

    公开(公告)号：US20120066690A1

    公开(公告)日：2012-03-15

    申请号：US12882892

    申请日：2010-09-15

    申请人： Gagan Gupta ,  Gurindar S. Sohi ,  Srinath Sridharan

    发明人： Gagan Gupta ,  Gurindar S. Sohi ,  Srinath Sridharan

    IPC分类号： G06F9/46

    CPC分类号： G06F9/526 ,  G06F8/45 ,  G06F9/46 ,  G06F9/50

    摘要： A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens.

    摘要翻译： 并行化程序的系统和方法将写入令牌和读取令牌分配给通过计算操作访问的数据对象。 在运行时间期间，用于计算操作的写入集合和读取集合被解析，并且只有在已经获得与分辨的写入和读取集合对应的数据对象的必要的令牌之后才执行计算操作。 数据对象可以具有无限制的读取令牌，但是只有单个写入令牌，并且只有在没有读取令牌未完成时才可以释放写入令牌。 数据对象提供等待列表，作为等待令牌的计算操作的有序队列。

    Gate netlist to register transfer level conversion tool
    9.
    发明授权
    Gate netlist to register transfer level conversion tool 失效
    Gate网表注册传输级转换工具

    公开(公告)号：US5867395A

    公开(公告)日：1999-02-02

    申请号：US668064

    申请日：1996-06-19

    申请人： Daniel Watkins ,  Gagan Gupta ,  Satish Venugopal ,  Kosala Abeywickrema ,  Venkat Mattela ,  Kumar Bhattaram

    发明人： Daniel Watkins ,  Gagan Gupta ,  Satish Venugopal ,  Kosala Abeywickrema ,  Venkat Mattela ,  Kumar Bhattaram

    IPC分类号： G06F17/50 ,  G06F17/00

    CPC分类号： G06F17/5045

    摘要： The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design. The present invention describes the method and apparatus to reverse-synthesize gate netlist level definitions into RTL definitions by parsing and analyzing the gate netlist level definition, generating an equivalent RTL definition, and verifying correctness of the RTL definition.

    摘要翻译： 本发明公开了一种将集成电路（IC）设计的门级网表定义反向合成到相同电路的对应寄存器传送级（RTL）定义的系统。 实现集成电路的典型过程是首先完成RTL设计，然后使用RTL设计来生成门级网表定义，最终制定针对特定工艺技术的布局级设计。 作为电路的一般描述的RTL设计定义可以被移植到不同的处理技术。 然而，作为电路的更具体或更低级别的门网络级别设计不容易移植到其他集成电路设计过程。 要将门网表级别设计移植到另一个进程技术中，门网网表应该被转换，或反向合成回到RTL级设计。 本发明描述了通过解析和分析门网表级别定义，生成等价的RTL定义和验证RTL定义的正确性来将门网表级别定义逆向合成到RTL定义中的方法和装置。