公开(公告)号：US6119092A

公开(公告)日：2000-09-12

申请号：US105614

申请日：1998-06-26

申请人： Arvind Patwardhan ,  Kosala Abeywickrema ,  Sophia Kao

发明人： Arvind Patwardhan ,  Kosala Abeywickrema ,  Sophia Kao

IPC分类号： G10L19/14 ,  G10L19/00 ,  G10L21/04

CPC分类号： G10L21/04

摘要： A multimedia decoder is provided with an audio decoder bypass module for forwarding undecoded audio bitstreams directly to external system components. In one embodiment, the multimedia decoder includes an audio decoder, and a bypass module. The audio decoder operates on the data in an audio bitstream buffer to convert at least a portion of the audio bitstream into a set of digital audio signals. The bypass module is configured to provide the full information content of the audio bitstream to an external system component which may be able to convert a greater portion of the audio bitstream into a second set of digital audio signals. As the audio decoder and bypass module each retrieve data from the audio bitstream buffer, they each use a pointer to track which location of the buffer to access next. The bypass module maintains a loose synchronization with the audio decoder by calculating the difference between the pointers and transmitting the current audio packet only if the magnitude of the difference doesn't exceed a predetermined threshold. If the bypass module is lagging behind the audio decoder by more than the threshold amount, then it skips ahead to the next audio packet. On the other hand, if the decoder is lagging behind the bypass module by more than the threshold amount, the bypass module waits for the audio decoder to catch up. This technique advantageously prevents detectable discrepancies in reproduced audio signals while allowing for system upgradability without significant increase in implementation cost.

摘要翻译： 多媒体解码器设置有用于将未解码的音频比特流直接转发到外部系统组件的音频解码器旁路模块。 在一个实施例中，多媒体解码器包括音频解码器和旁路模块。 音频解码器对音频比特流缓冲器中的数据进行操作，以将至少一部分音频比特流转换成一组数字音频信号。 旁路模块被配置为将音频比特流的全部信息内容提供给外部系统组件，该外部系统组件可能能够将较大部分的音频比特流转换为第二组数字音频信号。 由于音频解码器和旁路模块每个从音频比特流缓冲器中检索数据，它们每个都使用指针来跟踪下一个要访问的缓冲器的哪个位置。 只有当差值不超过预定阈值时，旁路模块通过计算指针之间​​的差异并发送当前音频分组来保持与音频解码器的松动同步。 如果旁路模块滞后于音频解码器超过阈值量，则它跳过下一个音频分组。 另一方面，如果解码器滞后于旁路模块超过阈值量，则旁路模块等待音频解码器赶上。 该技术有利地防止再现的音频信号中的可检测到的差异，同时允许系统升级而不显着增加实现成本。

公开(公告)号：US5867395A

公开(公告)日：1999-02-02

申请号：US668064

申请日：1996-06-19

申请人： Daniel Watkins ,  Gagan Gupta ,  Satish Venugopal ,  Kosala Abeywickrema ,  Venkat Mattela ,  Kumar Bhattaram

发明人： Daniel Watkins ,  Gagan Gupta ,  Satish Venugopal ,  Kosala Abeywickrema ,  Venkat Mattela ,  Kumar Bhattaram

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5045

摘要： The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design. The present invention describes the method and apparatus to reverse-synthesize gate netlist level definitions into RTL definitions by parsing and analyzing the gate netlist level definition, generating an equivalent RTL definition, and verifying correctness of the RTL definition.

摘要翻译： 本发明公开了一种将集成电路（IC）设计的门级网表定义反向合成到相同电路的对应寄存器传送级（RTL）定义的系统。 实现集成电路的典型过程是首先完成RTL设计，然后使用RTL设计来生成门级网表定义，最终制定针对特定工艺技术的布局级设计。 作为电路的一般描述的RTL设计定义可以被移植到不同的处理技术。 然而，作为电路的更具体或更低级别的门网络级别设计不容易移植到其他集成电路设计过程。 要将门网表级别设计移植到另一个进程技术中，门网网表应该被转换，或反向合成回到RTL级设计。 本发明描述了通过解析和分析门网表级别定义，生成等价的RTL定义和验证RTL定义的正确性来将门网表级别定义逆向合成到RTL定义中的方法和装置。