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    System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens
    5.
    发明申请
    System and Method Providing Run-Time Parallelization of Computer Software Using Data Associated Tokens 有权
    使用数据关联令牌提供计算机软件的运行时并行化的系统和方法

    公开(公告)号：US20120066690A1

    公开(公告)日：2012-03-15

    申请号：US12882892

    申请日：2010-09-15

    申请人： Gagan Gupta ,  Gurindar S. Sohi ,  Srinath Sridharan

    发明人： Gagan Gupta ,  Gurindar S. Sohi ,  Srinath Sridharan

    IPC分类号： G06F9/46

    CPC分类号： G06F9/526 ,  G06F8/45 ,  G06F9/46 ,  G06F9/50

    摘要： A system and method of parallelizing programs assigns write tokens and read tokens to data objects accessed by computational operations. During run time, the write sets and read sets for computational operations are resolved and the computational operations executed only after they have obtained the necessary tokens for data objects corresponding to the resolved write and read sets. A data object may have unlimited read tokens but only a single write token and the write token may be released only if no read tokens are outstanding. Data objects provide a wait list which serves as an ordered queue for computational operations waiting for tokens.

    摘要翻译： 并行化程序的系统和方法将写入令牌和读取令牌分配给通过计算操作访问的数据对象。 在运行时间期间，用于计算操作的写入集合和读取集合被解析，并且只有在已经获得与分辨的写入和读取集合对应的数据对象的必要的令牌之后才执行计算操作。 数据对象可以具有无限制的读取令牌，但是只有单个写入令牌，并且只有在没有读取令牌未完成时才可以释放写入令牌。 数据对象提供等待列表，作为等待令牌的计算操作的有序队列。

    Computer with dynamic instruction reuse
    6.
    发明授权
    Computer with dynamic instruction reuse 失效
    具有动态指令重用的计算机

    公开(公告)号：US5845103A

    公开(公告)日：1998-12-01

    申请号：US876137

    申请日：1997-06-13

    申请人： Avinash Sodani ,  Gurindar S. Sohi

    发明人： Avinash Sodani ,  Gurindar S. Sohi

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

    摘要： A computer architecture allowing reuse of previously determined instruction results, indexes instruction results according to instruction addresses. The continued validity of operand values in registers or memory for the instructions is determined prior to the fetching of any given instruction by an invalidation system which detects an intervening register or memory write. Thus, the need to evaluate the operand values themselves which would delay execution is avoided. In one embodiment, dependencies for operands between instructions are recorded so as to avoid invalidating instructions having operand register or memory locations which are overwritten when the overwriting will be corrected by an intervening instruction immediately preceding the dependent instructions.

    摘要翻译： 允许重新使用先前确定的指令结果的计算机架构，根据指令地址对指令结果进行索引。 在通过检测中间寄存器或存储器写入的无效系统取出任何给定指令之前，确定指令的寄存器或存储器中操作数值的持续有效性。 因此，避免了对延迟执行的操作数值本身的评估的需要。 在一个实施例中，记录指令之间的操作数的依赖关系，以避免使具有操作数寄存器或存储器位置的指令无效，当重写将通过在依赖指令之前的中间指令进行校正时被重写。

    Method and apparatus for parallel execution of computer software using a distilled program
    9.
    发明授权
    Method and apparatus for parallel execution of computer software using a distilled program 有权
    使用蒸馏程序并行执行计算机软件的方法和装置

    公开(公告)号：US06944754B2

    公开(公告)日：2005-09-13

    申请号：US10263514

    申请日：2002-10-02

    申请人： Craig Buchanan Zilles ,  Gurindar S. Sohi

    发明人： Craig Buchanan Zilles ,  Gurindar S. Sohi

    IPC分类号： G06F9/00 ,  G06F9/44

    CPC分类号： G06F8/443 ,  G06F8/456

    摘要： Parallelization of a program is performed by creating a distilled version of the program having higher execution speed but with unverified execution. The distilled program is executed rapidly to create state snapshots of the program that may be forwarded to secondary processors for execution of the actual program in parallel with other secondary processors similarly allocated. Each state snapshot is verified as the task is executed on a secondary processor by the preceding processor. The degree of parallelization is limited only by the speed up of the distilled program.

    摘要翻译： 通过创建具有较高执行速度但具有未经验证的执行的程序的蒸馏版本来执行程序的并行化。 快速执行蒸馏程序以创建程序的状态快照，该状态快照可以被转发到二级处理器，以与其他类似分配的其他辅助处理器并行执行实际程序。 当前处理器在二级处理器上执行任务时，会验证每个状态快照。 并行程度仅受蒸馏程序加速的限制。

    Electronic processor providing direct data transfer between linked data consuming instructions
    10.
    发明授权
    Electronic processor providing direct data transfer between linked data consuming instructions 有权
    电子处理器在链接的数据消耗指令之间提供直接数据传输

    公开(公告)号：US06658554B1

    公开(公告)日：2003-12-02

    申请号：US09418522

    申请日：1999-10-14

    申请人： Andreas I. Moshovos ,  Gurindar S. Sohi

    发明人： Andreas I. Moshovos ,  Gurindar S. Sohi

    IPC分类号： G06F930

    CPC分类号： G06F9/3834 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3859

    摘要： A data dependence prediction technique is used to establish linkage between two instructions using data so that accessing the data from memory may be bypassed. Instead, the data retrieved in the first data using instruction is temporarily stored in a local register to be used by the second data using instruction. Parallel processing techniques of squashing are used in the event that the prediction is erroneous.

    摘要翻译： 使用数据相关性预测技术来建立使用数据的两条指令之间的链接，从而可以绕过存储器中的数据。 相反，使用指令在第一数据中检索的数据被临时存储在本地寄存器中，以由第二数据使用指令使用。 在预测错误的情况下使用挤压的并行处理技术。