公开(公告)号：US5781752A

公开(公告)日：1998-07-14

申请号：US773992

申请日：1996-12-26

Applicant: Andreas I. Moshovos ,  Scott E. Breach ,  Terani N. Vijaykumar ,  Gurindar S. Sohi

Inventor： Andreas I. Moshovos ,  Scott E. Breach ,  Terani N. Vijaykumar ,  Gurindar S. Sohi

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3834 ,  G06F9/3842

Abstract: A predictor circuit permits advanced execution of instructions depending for their data on previous instructions by predicting such dependencies based on previous mis-speculations detected at the final stages of processing. Synchronization of dependent instructions is provided by a table creating entries for each instance of potential dependency. Table entries are created and deleted dynamically to limit total memory requirements.

Abstract translation: 根据在处理的最后阶段检测到的先前错误猜测，预测器电路允许根据先前指令的数据来高级执行指令。 相关指令的同步由为潜在依赖性的每个实例创建条目的表提供。 创建和删除表条目以限制总内存要求。

公开(公告)号：US07024533B2

公开(公告)日：2006-04-04

申请号：US10441451

申请日：2003-05-20

Applicant: Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

Inventor： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

IPC: G06F12/00

CPC classification number: G06F13/1689

Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

公开(公告)号：US06636955B1

公开(公告)日：2003-10-21

申请号：US09652480

申请日：2000-08-31

Applicant: Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

Inventor： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

IPC: G06F1200

CPC classification number: G06F13/1689

Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

Abstract translation: 计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。 存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。 存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。 该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。 卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。 指针优选地是根据两个不同的时钟信号递增的自由运行指针。 负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。 卸载指针根据计算机系统本身产生的时钟增加。 因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。 在系统初始化期间，指针是同步的。 初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。

公开(公告)号：US06668335B1

公开(公告)日：2003-12-23

申请号：US09653643

申请日：2000-08-31

Applicant: Scott E. Breach ,  John Eble ,  Arvind Kumar ,  Richard E. Kessler ,  Darrel Donaldson ,  David W. Hartwell

Inventor： Scott E. Breach ,  John Eble ,  Arvind Kumar ,  Richard E. Kessler ,  Darrel Donaldson ,  David W. Hartwell

IPC: G06F104

CPC classification number: H04L45/00 ,  G06F1/10

Abstract: A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along different paths. A forwarded clock signal is sent with each bundle. The processors operate with a clock frequency that is roughly three times as fast as the clock frequency of the forwarded clock signal. Data is transmitted on both rising and falling edges of the clock. The receiving processor comprises a recovery circuit to which it pulls the asynchronous data into the processor clock domain. The recovery circuit comprises a delay locked loop circuit configured to create a delayed copy of the clock signal with clock edges that are aligned with the center of the data window for the transmitted data.

Abstract translation: 一种系统，包括被配置为在发送和接收处理器之间传送分组的处理器之间的通信链路。 通信链路包括用于分组中的每个比特的传导路径，并且路径被分组成分开的分组并沿着不同的路径路由。 每个包发送转发的时钟信号。 处理器的工作时钟频率大约是转发时钟信号的时钟频率的三倍。 数据在时钟的上升沿和下降沿都传输。 接收处理器包括一个恢复电路，它将异步数据拉入处理器时钟域。 恢复电路包括延迟锁定环路电路，其被配置为创建时钟信号的延迟副本，其中时钟沿与发送数据的数据窗口的中心对准。