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    System and method to provide non-coherent access to a coherent memory system
    3.
    发明授权
    System and method to provide non-coherent access to a coherent memory system 有权
    提供对相干存储器系统的非相干访问的系统和方法

    公开(公告)号：US08850125B2

    公开(公告)日：2014-09-30

    申请号：US13280756

    申请日：2011-10-25

    Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

    Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

    IPC: G06F13/00 ,  G06F13/28 ,  G06F12/08

    CPC classification number: G06F12/0888 ,  G06F12/08 ,  G06F12/0831

    Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

    Abstract translation: 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访​​问路径和到存储器的旁路高速缓存访​​问路径，接收从旁路高速缓存访​​问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访​​问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访​​问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。

    Direct access to low-latency memory
    8.
    发明授权
    Direct access to low-latency memory 有权
    直接访问低延迟内存

    公开(公告)号：US07594081B2

    公开(公告)日：2009-09-22

    申请号：US11024002

    申请日：2004-12-28

    Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

    Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

    CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

    Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

    Abstract translation: 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

    Selective replication of data structures
    9.
    发明授权
    Selective replication of data structures 有权
    数据结构的选择性复制

    公开(公告)号：US07558925B2

    公开(公告)日：2009-07-07

    申请号：US11335189

    申请日：2006-01-18

    Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

    Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

    IPC: G06F12/02

    CPC classification number: G06F12/06 ,  G06F12/0653 ,  G06F2212/174

    Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

    Abstract translation: 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
    10.
    发明授权
    Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效

    公开(公告)号：US07024533B2

    公开(公告)日：2006-04-04

    申请号：US10441451

    申请日：2003-05-20

    Applicant: Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    Inventor： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

    IPC: G06F12/00

    CPC classification number: G06F13/1689

    Abstract: A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

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