公开(公告)号：US07594081B2

公开(公告)日：2009-09-22

申请号：US11024002

申请日：2004-12-28

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F9/3824 ,  G06F9/3885 ,  G06F12/0888

Abstract: A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

Abstract translation: 提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。 该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。 系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。 低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。 非普通的加载/存储指令可以是协处理器指令。 存储器可以是低延迟型存储器。 处理器可以包括多个处理器核。

公开(公告)号：US07558925B2

公开(公告)日：2009-07-07

申请号：US11335189

申请日：2006-01-18

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler

IPC: G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0653 ,  G06F2212/174

Abstract: Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).

Abstract translation: 提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。 存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。 在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。 可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。 受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

公开(公告)号：US08301788B2

公开(公告)日：2012-10-30

申请号：US11220899

申请日：2005-09-07

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F15/16 ,  G06F15/173 ,  H04L12/28 ,  H04J3/06

CPC classification number: G06F9/30003 ,  H04L1/0045

Abstract: A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

Abstract translation: 描述了一种用于遍历确定性有限自动机（DFA）图的计算机可读指令，以便在即将进行的分组数据中实时地执行模式搜索。 该指令包括一个或多个预定义字段。 其中一个字段包括用于标识几个先前存储的DFA图形之一的DFA图形标识符。 另一个领域包括用于使用所识别的DFA图形来识别要处理的输入数据的输入参考。 另一个领域包括用于存储响应于经处理的输入数据生成的结果的输出参考。 这些指令被转发到适用于使用识别的DFA图处理输入数据的DFA引擎，并根据输出参考的指示提供结果。

公开(公告)号：US08392590B2

公开(公告)日：2013-03-05

申请号：US11221408

申请日：2005-09-07

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F15/16 ,  G06F17/28

CPC classification number: H04L49/90 ,  G06F15/7846 ,  H04L29/06 ,  H04L63/02 ,  H04L63/04 ,  H04L63/145 ,  H04L63/164 ,  H04L69/12

Abstract: A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.

Abstract translation: 用于实时传入传入分组数据的运行确定性有限自动机（DFA）图的处理器。 所述处理器包括至少一个处理器核心和与所述至少一个处理器核心异步操作的DFA模块，用于使用存储在高速缓存相干存储器中的分组数据遍历存储在非高速缓冲存储器中的至少一个DFA图形。

公开(公告)号：US08560757B2

公开(公告)日：2013-10-15

申请号：US13280738

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

IPC: G06F12/00

CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

Abstract: In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract translation: 在一个实施例中，系统包括分布到由子集索引识别的子集中的存储器端口，其中每个存储器端口基于相应的工作负载具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址并参考图形数据的读取请求。 第一地址散列单元基于虚拟存储器地址将复制因子转换为相应的子集索引，并且参考由相应子集索引指示的子集内的存储器端口中的图形数据将虚拟存储器地址转换为基于硬件的存储器地址 。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

公开(公告)号：US20130103904A1

公开(公告)日：2013-04-25

申请号：US13280738

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1018 ,  G06F12/0292 ,  G06F12/06 ,  G06F2212/174 ,  G06F2212/2532

Abstract: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract translation: 在一个实施例中，系统包括分布到多个子集中的多个存储器端口，每个子集由子集索引标识，每个存储器端口具有单独的等待时间。 该系统还包括第一地址哈希单元，其被配置为接收包括与复制因子相关联的虚拟存储器地址的读取请求，并且参考图形数据。 第一地址散列单元基于虚拟存储器地址将复制因子转换为对应的子集索引，并将虚拟存储器地址转换为基于硬件的存储器地址，该存储器地址涉及由相应子集指示的子集内的存储器端口中的图形数据 指数。 该系统还包括存储器复制控制器，其被配置为将读取请求引导到基于硬件的地址到具有最低个人等待时间的相应子集索引指示的子集内的存储器端口之一。

公开(公告)号：US07814310B2

公开(公告)日：2010-10-12

申请号：US10411967

申请日：2003-04-12

Applicant: Gregg A. Bouchard ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: H04L29/06

CPC classification number: H04L63/0485 ,  H04L63/1466 ,  H04L63/164

Abstract: A method and apparatus for optimizing IPsec processing by providing execution units with windowing data during prefetch and managing coherency of security association data by management of security association accesses. Providing execution units with windowing data allows initial parallel processing of IPsec packets. The security association access ordering apparatus serializes access to the dynamic section of security association data according to packet order arrival while otherwise allowing parallel processing of the IPsec packet by multiple execution units in a security processor.

Abstract translation: 一种通过在预取期间向执行单元提供窗口数据并通过管理安全关联访问来管理安全关联数据的一致性来优化IPsec处理的方法和装置。 为执行单元提供窗口数据允许IPsec数据包的初始并行处理。 安全关联访问排序装置根据分组顺序序列化对安全关联数据的动态部分的访问，而另外允许在安全处理器中由多个执行单元并行处理IPsec分组。

公开(公告)号：US06920512B2

公开(公告)日：2005-07-19

申请号：US10780395

申请日：2004-02-17

Applicant: Maurice B. Steinman ,  Richard E. Kessler ,  Gregg A. Bouchard

Inventor： Maurice B. Steinman ,  Richard E. Kessler ,  Gregg A. Bouchard

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4059

Abstract: An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.

Abstract translation: 一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。 特别地，通过智能地管理双向总线上的读取和写入，可以减少总线延迟，同时仍然确保没有总线争用或读取/写入饥饿。 这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。

公开(公告)号：US06662265B1

公开(公告)日：2003-12-09

申请号：US09652704

申请日：2000-08-31

Applicant: Richard E. Kessler ,  Maurice B. Steinman ,  Michael S. Bertone ,  Peter J. Bannon ,  Gregg A. Bouchard

Inventor： Richard E. Kessler ,  Maurice B. Steinman ,  Michael S. Bertone ,  Peter J. Bannon ,  Gregg A. Bouchard

IPC: G06F1200

CPC classification number: G06F12/0215 ,  G06F13/1631

Abstract: A system and method is disclosed to track a large number of open pages in a computer memory system. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. A RIMM module containing RDRAM devices is coupled to each processor, each RDRAM containing a plurality of memory banks. The page table increases system memory performance by tracking a large number of open memory pages. Associated with the page table is a bank active table that indicates the memory banks in each RDRAM device having open memory pages. The page table enqueues accesses to the RIMM module in a precharge queue resulting from a page miss caused by the address of an open memory page occupying the same row of the page table as the address of the system memory access resulting in the page miss. The page table also enqueues accesses to system memory in a Row-address-select (“RAS”) queue resulting from a page miss caused by a row of the page table not containing any open memory page address. The page table enqueues accesses to system memory resulting in page hits to open memory pages in a Column-address-select (“CAS”) queue. An entry in the precharge queue is then enqueued into the RAS queue. An entry in the RAS queue after completion is enqueued into the CAS Read or CAS Write queue.

Abstract translation: 公开了一种在计算机存储器系统中跟踪大量打开页面的系统和方法。 计算机系统包含一个或多个处理器，每个处理器包括包含页表的存储器控​​制器，所述页表被组织成多行，每行能够存储打开存储器页的地址。 包含RDRAM设备的RIMM模块耦合到每个处理器，每个RDRAM包含多个存储器组。 页面表通过跟踪大量的开放内存页面来增加系统内存性能。 与页表相关联的是一个存储区活动表，指示每个具有打开存储器页的RDRAM设备中的存储体。 页表格排队访问预充电队列中的RIMM模块，这是由于打开的内存页面的地址与页表的同一行的地址导致的页错误导致的系统内存访问的地址导致页错过。 页表还对由行页地址选择（“RAS”）队列访问系统内存进行排队，这是由于不包含任何打开的内存页地址的页表的行引起的页错误导致的。 页面表格对对系统内存的访问进行排队，导致页面命中，以打开列地址选择（“CAS”）队列中的内存页面。 然后将预充电队列中的条目排入RAS队列。 完成后RAS队列中的条目排入CAS读取或CAS写入队列。

公开(公告)号：US08850125B2

公开(公告)日：2014-09-30

申请号：US13280756

申请日：2011-10-25

Applicant: Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

Inventor： Jeffrey Pangborn ,  Gregg A. Bouchard ,  Rajan Goyal ,  Richard E. Kessler ,  Aseem Maheshwari

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/08 ,  G06F12/0831

Abstract: In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.

Abstract translation: 在一个实施例中，系统包括存储器和存储器控制器，其提供到存储器的高速缓存访​​问路径和到存储器的旁路高速缓存访​​问路径，接收从旁路高速缓存访​​问路径上的存储器读取图形数据的请求，以及 接收从缓存访问路径上的内存中读取非图形数据的请求。 一种方法包括在存储器控制器处接收来自旁路高速缓存访​​问路径上的存储器的图形数据的请求，在存储器控制器处接收请求以通过高速缓存访​​问路径从存储器读取非图形数据， 在内存控制器中，在使用仲裁的请求中。