公开(公告)号：US12132581B2

公开(公告)日：2024-10-29

申请号：US17103802

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

CPC classification number: H04L12/1868 ,  G06F12/0238 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/4059 ,  H04L12/5601 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  G06F2213/28 ,  H04L2012/562

Abstract: Examples described herein includes an apparatus comprising: a network interface configured to: receive a request to copy data from a local memory to a remote memory; based on a configuration that the network interface is to manage a cache store the data into the cache and record that the data is stored in the cache. In some examples, store the data in the cache comprises store most recently evicted data from the local memory into the cache. In some examples, the network interface is to store data evicted from the local memory that is not stored into the cache into one or more remote memories.

公开(公告)号：US20240345977A1

公开(公告)日：2024-10-17

申请号：US18134994

申请日：2023-04-14

Applicant: XILINX, INC.

Inventor： Dinesh D. GAITONDE ,  Aashish TRIPATHI ,  Ashit DEBNATH ,  Davis Boyd MOORE ,  Maithilee Rajendra KULKARNI ,  Abhishek Kumar JAIN

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4068

Abstract: A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

公开(公告)号：US12003346B2

公开(公告)日：2024-06-04

申请号：US17132340

申请日：2020-12-23

Applicant: Maxim Integrated Products, Inc.

Inventor： Wuguang Liu ,  Stewart Merkel

IPC: H04L12/40 ,  G06F1/26 ,  G06F13/40 ,  H02J7/00 ,  H04B3/54

CPC classification number: H04L12/40045 ,  G06F1/266 ,  G06F13/4027 ,  G06F13/4059 ,  H02J7/007 ,  H04B3/548 ,  H04L12/40032 ,  H02J2310/22

Abstract: Described herein are embodiments for dual-port communication and power delivery for one-wire applications. Embodiments of one-wire bridge devices are disclosed to provide a dual-port link for two one-wire masters to communicate with one another in a multi-voltage system while intermittently allowing charging voltage. The configuration may be used to set a bidirectional pass through mode that allows level shifted fast logic signals to pass through the two one-wire links. A timer may also be configurable to time-out the pass through mode from edge in-activity. Power may be derived for operation directly from one of the links, eliminating the need for an external power supply when local power is not available. When local power is available, the other one-wire link provides local access and the pass through mode. Such configurations make it easy for a two-contact solution to be both a communication channel and a power supply for battery charging.

公开(公告)号：US11762663B2

公开(公告)日：2023-09-19

申请号：US18071627

申请日：2022-11-30

Applicant: SOFTGEAR CO., LTD.

Inventor： Naoki Miyanaga

IPC: G06F9/38 ,  G06F9/50 ,  G06F3/06 ,  G06F13/40

CPC classification number: G06F9/381 ,  G06F9/5027 ,  G06F3/0656 ,  G06F13/4059

Abstract: Provided are an information processing program, an information processing device, and an information processing method that enable application processing and data transmission in a non-blocking manner to increase a communication speed. A server device includes buffering means configured to accumulate events, socket writing means configured to process the events, and flag management means configured to exclusively set a flag. The socket writing means includes socket write request means and callback processing means. The flag management means exclusively sets the flag at a timing before the event processing requested by the socket write request means starts, and releases the flag at a timing after the processing by the callback processing means ends. The socket write request means receives a call, and in a case where the flag is set, the events accumulated by the buffering means are processed.

公开(公告)号：US11726947B2

公开(公告)日：2023-08-15

申请号：US17081595

申请日：2020-10-27

Applicant: SK hynix Inc.

Inventor： Dae Sik Park ,  Byung Cheol Kang ,  Seung Duk Cho

IPC: G06F13/42 ,  G06F1/08 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F1/08 ,  G06F13/4022 ,  G06F13/4059

Abstract: A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes initializing one or more parameters associated with clock signals for a data transmission or reception of the interface device, checking whether the interface device is in a predetermined mode for adjusting the one or more parameters, adjusting, upon determination that the interface device is in the predetermined mode, the one or more parameters associated with the clock signals of the interface device based on how much of the first buffer or the second buffer is filled with data, and performing the data transmission or reception based on the adjusted one or more parameters associated with the clock signals.

公开(公告)号：US11726937B2

公开(公告)日：2023-08-15

申请号：US17447832

申请日：2021-09-16

Applicant: Graphcore Limited

Inventor： Graham Bernard Cunningham ,  Stephen Felix

IPC: G06F13/364 ,  G06F9/52 ,  G06F13/40

CPC classification number: G06F13/364 ,  G06F9/522 ,  G06F13/4059

Abstract: A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.

公开(公告)号：US20230244623A1

公开(公告)日：2023-08-03

申请号：US17545930

申请日：2021-12-08

Applicant: ATI Technologies ULC

Inventor： Michael E. McLean ,  Philip Ng

IPC: G06F13/372 ,  G06F13/364 ,  G06F13/366 ,  G06F13/40 ,  G06F9/48

CPC classification number: G06F13/372 ,  G06F9/4812 ,  G06F13/364 ,  G06F13/366 ,  G06F13/4059

Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window. This arbitration process continues for successive arbitration windows, oscillating between incrementing and decrementing the masking index value during the successive arbitration windows.

公开(公告)号：US11693809B2

公开(公告)日：2023-07-04

申请号：US17577934

申请日：2022-01-18

Applicant: Liquid-Markets-Holdings, Incorporated

Inventor： Seth Gregory Friedman ,  Alexis Nicolas Jean Gryta ,  Thierry Gibralta

IPC: G06F13/40 ,  G06F13/28

CPC classification number: G06F13/404 ,  G06F13/28 ,  G06F13/4018 ,  G06F13/4059 ,  G06F13/4072 ,  G06F2213/0026 ,  G06F2213/16 ,  G06F2213/2806

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

公开(公告)号：US20230205585A1

公开(公告)日：2023-06-29

申请号：US18084013

申请日：2022-12-19

Applicant: SambaNova Systems, Inc.

Inventor： Ranen CHATTERJEE ,  Ravinder KUMAR ,  Raghunath SHENBAGAM ,  Maran WILSON ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Arjun SABNIS ,  Yannan CHEN

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F13/40

CPC classification number: G06F9/5016 ,  G06F9/545 ,  G06F9/30123 ,  G06F13/4059 ,  G06F2209/5011

Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.

公开(公告)号：US11687479B2

公开(公告)日：2023-06-27

申请号：US17482528

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Jie Zheng ,  Deanna Postles Dunn Berger ,  Chad G. Wilson ,  Poornima P Sulibele ,  James Franklin Driftmyer

IPC: G06F13/40 ,  G06F1/24 ,  G06F13/362

CPC classification number: G06F13/4059 ,  G06F1/24 ,  G06F13/362 ,  G06F13/4045

Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.