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公开(公告)号：US11687479B2
公开(公告)日：2023-06-27
申请号：US17482528
申请日：2021-09-23
Applicant: International Business Machines Corporation
Inventor： Jie Zheng , Deanna Postles Dunn Berger , Chad G. Wilson , Poornima P Sulibele , James Franklin Driftmyer
IPC: G06F13/40 , G06F1/24 , G06F13/362
CPC classification number: G06F13/4059 , G06F1/24 , G06F13/362 , G06F13/4045
Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.
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2.发明授权
公开(公告)号：US11687254B2
公开(公告)日：2023-06-27
申请号：US16676962
申请日：2019-11-07
Applicant: International Business Machines Corporation
Inventor： Steven R. Carlough , Susan M. Eickhoff , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
IPC: G06F3/06
CPC classification number: G06F3/0626 , G06F3/065 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/0685
Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
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公开(公告)号：US11042325B2
公开(公告)日：2021-06-22
申请号：US16532041
申请日：2019-08-05
Applicant: International Business Machines Corporation
Inventor： Jie Zheng , Steven R. Carlough , William J. Starke , Jeffrey A. Stuecheli , Stephen J. Powell
Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.
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公开(公告)号：US10976939B2
公开(公告)日：2021-04-13
申请号：US16598103
申请日：2019-10-10
Applicant: International Business Machines Corporation
Inventor： Steven R. Carlough , Susan M. Eickhoff , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
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公开(公告)号：US20200097214A1
公开(公告)日：2020-03-26
申请号：US16140780
申请日：2018-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Jie Zheng , Stephen J. Powell , Steven R. Carlough , Susan M. Eickhoff
Abstract: An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.
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6.发明申请
公开(公告)号：US20200073565A1
公开(公告)日：2020-03-05
申请号：US16676962
申请日：2019-11-07
Applicant: International Business Machines Corporation
Inventor： Steven R. Carlough , Susan M. Eickhoff , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
IPC: G06F3/06
Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
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7.发明申请
公开(公告)号：US20190163383A1
公开(公告)日：2019-05-30
申请号：US15825894
申请日：2017-11-29
Applicant: International Business Machines Corporation
Inventor： Steven R. Carlough , Susan M. Eickhoff , Warren E. Maule , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
IPC: G06F3/06
CPC classification number: G11C7/109 , G06F3/0611 , G06F3/0626 , G06F3/0658 , G06F3/0659 , G06F3/0685 , G06F12/08 , G11C5/04 , G11C7/1003 , G11C7/1078 , G11C7/22 , G11C2207/2245
Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
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公开(公告)号：US20180102917A1
公开(公告)日：2018-04-12
申请号：US15839350
申请日：2017-12-12
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Andrew R. Ranck , Mushfiq U. Saleheen , Jie Zheng
IPC: H04L12/46 , H04L12/861 , H04L12/40 , G06F13/40
CPC classification number: H04L12/46 , G06F13/4027 , H04L12/40 , H04L12/4625 , H04L49/90
Abstract: Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).
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公开(公告)号：US20180091363A1
公开(公告)日：2018-03-29
申请号：US15432267
申请日：2017-02-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Howard M. Haynie , Donald Jung , Jeffrey M. Turner , Jie Zheng
CPC classification number: H04L41/082 , G06F8/65 , G06F8/654 , G06F15/7871 , H04L67/303 , H04L69/30
Abstract: Examples of techniques for upgrading a descriptor engine for a network interface card (NIC) are disclosed. An example method may include: quiescing a transmit stream to the NIC; stopping a descriptor engine from providing new receive descriptors to the NIC; creating a copy in a memory of any receive descriptors already available to the NIC prior to the stopping the descriptor engine; setting a controller to redirect inbound traffic to the memory; logging a current configuration, state, and receive pointers of the descriptor engine; updating the descriptor engine; restoring a transmit configuration and a transmit state of the descriptor engine; and enabling a transmit stream of a data router such that transmit packets are created by the descriptor engine for transmission by the NIC.
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公开(公告)号：US20230085998A1
公开(公告)日：2023-03-23
申请号：US17482528
申请日：2021-09-23
Applicant: International Business Machines Corporation
Inventor： Jie Zheng , Deanna Postles Dunn Berger , Chad G. Wilson , Poornima P Sulibele , James Franklin Driftmyer
IPC: G06F13/40 , G06F13/362 , G06F1/24
Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.
