公开(公告)号：US20230333879A1

公开(公告)日：2023-10-19

申请号：US18133632

申请日：2023-04-12

申请人： SambaNova Systems, Inc.

发明人： Arnav GOEL ,  Ravinder KUMAR ,  Qi ZHENG ,  Milad SHARIF ,  Jiayu BAI ,  Neal SANGHVI

IPC分类号： G06F9/48 ,  G06F9/445 ,  G06F9/50

CPC分类号： G06F9/4843 ,  G06F9/44505 ,  G06F9/5016

摘要： A data processing system is presented that is configured as a server in a client-server configuration for executing applications that a client in the client-server configuration can offload as execution tasks for execution on the server. The data processing system includes a reconfigurable processor, a storage device that stores configuration files for the applications, and a host processor that is coupled to the storage device and to the reconfigurable processor. The host processor is configured to receive an execution task of the execution tasks with an identifier of an application from the client, retrieve a configuration file that is associated with the application from the storage device using the identifier of the application, configure the reconfigurable processor with the configuration file, and start execution of the application on the reconfigurable processor, whereby the reconfigurable processor provides output data of the execution of the application to the client.

公开(公告)号：US20230205613A1

公开(公告)日：2023-06-29

申请号：US18087104

申请日：2022-12-22

申请人： SambaNova Systems, Inc.

发明人： Joshua POLZIN ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Qi ZHENG ,  Maran WILSON ,  Neal SANGHVI

IPC分类号： G06F9/54 ,  G06F9/50

CPC分类号： G06F9/544 ,  G06F9/5016

摘要： A method of pipelining execution stages of a pipelined application can comprise a Buffer Pipeline Manager (BPM) of a Buffer Pipelined Application computing System (BPAS) allocating pipeline buffers, configuring access to the pipeline buffers by stage processors of the system, transferring buffers from one stage processor to a successor stage processor, and transferring data from a buffer in one memory to a buffer in an alternative memory. The BPM can allocate the buffers based on execution parameters associated with the pipelined application and/or stage processors. The BPM can transfer data to a buffer in an alternative memory based on performance, capacity, and/or topological attributes of the memories and/or processors utilizing the memories. The BPM can perform operations of the method responsive to interfaces of a Pipeline Programming Interface (PPI). A BPAS can comprise hardware processors, physical memories, stage processors, an application execution program, the PPI, and the BPM.

公开(公告)号：US20240338297A1

公开(公告)日：2024-10-10

申请号：US18244677

申请日：2023-09-11

申请人： SambaNova Systems, Inc.

发明人： Arnav GOEL ,  Qi ZHENG ,  Guoyao FENG ,  Chen YANG ,  Jianding LUO

IPC分类号： G06F11/36 ,  G06F15/78

CPC分类号： G06F11/3644 ,  G06F11/3636 ,  G06F15/7871

摘要： A data processing system includes an array of reconfigurable units and a compiler configured to generate one or more configuration files for an application for execution on one or more reconfigurable processors. The data processing system further includes an execution flow logic which is configured to cause execution of the configuration files on the reconfigurable processors to be dependent upon one or more breakpoint conditions. The data processing further includes a runtime logic configured to execute the configuration files depending upon the breakpoint conditions. A corresponding method is also disclosed herein.

公开(公告)号：US20220269534A1

公开(公告)日：2022-08-25

申请号：US17185264

申请日：2021-02-25

申请人： SambaNova Systems, Inc.

发明人： Anand MISRA ,  Arnav GOEL ,  Qi ZHENG ,  Raghunath SHENBAGAM ,  Ravinder KUMAR

IPC分类号： G06F9/48 ,  G06F9/38

摘要： A method for executing applications in a system comprising general hardware and reconfigurable hardware includes accessing a first execution file comprising metadata storing a first priority indicator associated with a first application, and a second execution file comprising metadata storing a second priority indicator associated with a second application. In an example, use of the reconfigurable hardware is interleaved between the first application and the second application, and the interleaving is scheduled to take into account (i) workload of the reconfigurable hardware and (ii) the first priority indicator and the second priority indicator associated with the first application and the second application, respectively. In an example, when the reconfigurable hardware is used by one of the first and second applications, the general hardware is used by another of the first and second applications.

公开(公告)号：US20220197712A1

公开(公告)日：2022-06-23

申请号：US17522682

申请日：2021-11-09

申请人： SambaNova Systems, Inc.

发明人： Ram SIVARAMAKRISHNAN ,  Sumti JAIRATH ,  Emre Ali BURHAN ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Ravinder KUMAR ,  Arnav GOEL ,  Ranen CHATTERJEE ,  Gregory Frederick GROHOSKI ,  Kin Hing LEUNG ,  Dawei HUANG ,  Manoj UNNIKRISHNAN ,  Martin Russell RAUMANN ,  Bandish B. SHAH

IPC分类号： G06F9/50 ,  G06F9/455

摘要： The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.

公开(公告)号：US20240273057A1

公开(公告)日：2024-08-15

申请号：US18635114

申请日：2024-04-15

申请人： SambaNova Systems, Inc.

发明人： Greg DYKEMA ,  Maran WILSON ,  Guoyao FENG ,  Kuan ZHOU ,  Tianyu SUN ,  Taylor LEE ,  Kin Hing LEUNG ,  Arnav GOEL ,  Conrad Alexander TURLIK ,  Milad SHARIF

IPC分类号： G06F15/80 ,  G06F8/41 ,  G06F15/78

CPC分类号： G06F15/8038 ,  G06F8/443 ,  G06F8/447 ,  G06F8/45 ,  G06F15/7867 ,  G06F15/80

摘要： A host system for executing an application on first and/or second reconfigurable processors is presented. The host system is operatively coupled to the first and second reconfigurable processors, whereby the first reconfigurable processors have a first architecture, and the second reconfigurable processors have a second architecture that is different than the first architecture. The host system allocates reconfigurable processors of the first and/or second reconfigurable processors for executing the application and includes an auto-discovery module that is configured to determine whether the allocated reconfigurable processors include at least one of the first reconfigurable processors.

公开(公告)号：US20240231903A1

公开(公告)日：2024-07-11

申请号：US18614639

申请日：2024-03-23

申请人： SambaNova Systems, Inc.

发明人： Qi ZHENG ,  Arnav GOEL ,  Conrad Alexander TURLIK ,  Guoyao FENG ,  Joshua Earle POLZIN ,  Fansheng CHENG ,  Ravinder KUMAR ,  Greg DYKEMA ,  Subhra MAZUMDAR ,  Milad SHARIF ,  Jiayu BAI ,  Neal SANGHVI ,  Arjun SABNIS ,  Letao CHEN

IPC分类号： G06F9/48 ,  G06F9/38

CPC分类号： G06F9/4881 ,  G06F9/3877

摘要： In a computer-implemented method a Dynamic Transfer Engine (DTE) included in a computing system receives a dynamic stimulus associated with transfer of stage data during execution of a dataflow application by the system. The DTE determines, based on source and destination devices of the transfer, a transfer method and a transfer channel to transfer the stage data between memories coupled to the source and destination devices. The DTE acquires, hardware resources of the computing system to transfer the stage using the channel and, initiates the transfer. A computer program product can cause one or more processors to perform the method. A computing system can comprise source and destination processors and memories, hardware channels to transfer data between the memories, a resource manager, and a DTE configured to perform the method.

公开(公告)号：US20230297527A1

公开(公告)日：2023-09-21

申请号：US18121224

申请日：2023-03-14

申请人： SambaNova Systems, Inc.

发明人： Conrad Alexander TURLIK ,  Sudhakar DINDUKURTI ,  Anand MISRA ,  Arjun SABNIS ,  Milad SHARIF ,  Ravinder KUMAR ,  Joshua Earle POLZIN ,  Arnav GOEL ,  Steven DAI

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F2213/3808

摘要： A system is presented that includes two data processing systems that are coupled via a network, each data processing system including a reconfigurable processor with a reconfigurable processor memory, a host that is coupled to the reconfigurable processor and that includes a host processor and a host memory that is coupled to the host processor, and a network interface controller (NIC) that is operatively coupled to the reconfigurable processor and to the host processor. The reconfigurable processor of one of the data processing systems is configured to implement a virtual function that uses a virtual address for a memory access operation. An application programming interface (API) in the host processor translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct memory access operation at the reconfigurable processor memory or the host memory of the other data processing system.

公开(公告)号：US20220197709A1

公开(公告)日：2022-06-23

申请号：US17522655

申请日：2021-11-09

申请人： SambaNova Systems, Inc.

发明人： Ram SIVARAMAKRISHNAN ,  Sumti JAIRATH ,  Emre Ali BURHAN ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Ravinder KUMAR ,  Arnav GOEL ,  Ranen CHATTERJEE ,  Gregory Frederick GROHOSKI ,  Kin Hing LEUNG ,  Dawei HUANG ,  Manoj UNNIKRISHNAN ,  Martin Russell RAUMANN ,  Bandish B. SHAH

IPC分类号： G06F9/50 ,  G06F9/455

摘要： The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.

公开(公告)号：US20240338340A1

公开(公告)日：2024-10-10

申请号：US18243994

申请日：2023-09-08

申请人： SambaNova Systems, Inc.

发明人： Arnav GOEL ,  Ravinder KUMAR ,  Arjun SABNIS ,  Qi ZHENG ,  Neal SANGHVI

IPC分类号： G06F15/80 ,  G06F15/82

CPC分类号： G06F15/80 ,  G06F15/825

摘要： A data processing system including an array of reconfigurable units and a compiler configured to generate to execute a dataflow graph of a user application is disclosed. The dataflow graph includes a sequence of temporal partitions, each temporal partition including a sequence of graph control operations. Also disclosed is an intelligent graph orchestration and execution engine (IGOEE) configured to receive an optimization objective from the complier. The optimization objective can be for minimizing execution time of the reconfigurable processor or maximizing computing resource utilization of the reconfigurable processor. The IGOEE can reorganize the sequence of temporal partitions and the sequence of graph control operations within each temporal partition to satisfy the optimization objective; and execute the reorganized dataflow graph on the reconfigurable processor. A corresponding method is also disclosed herein.