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公开(公告)号：US20220197712A1
公开(公告)日：2022-06-23
申请号：US17522682
申请日：2021-11-09
发明人： Ram SIVARAMAKRISHNAN , Sumti JAIRATH , Emre Ali BURHAN , Manish K. SHAH , Raghu PRABHAKAR , Ravinder KUMAR , Arnav GOEL , Ranen CHATTERJEE , Gregory Frederick GROHOSKI , Kin Hing LEUNG , Dawei HUANG , Manoj UNNIKRISHNAN , Martin Russell RAUMANN , Bandish B. SHAH
摘要： The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor on a first node, and a second host processor on a second node. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second host processor using one or more SmartNIC buffers.
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公开(公告)号：US20220197709A1
公开(公告)日：2022-06-23
申请号：US17522655
申请日：2021-11-09
发明人： Ram SIVARAMAKRISHNAN , Sumti JAIRATH , Emre Ali BURHAN , Manish K. SHAH , Raghu PRABHAKAR , Ravinder KUMAR , Arnav GOEL , Ranen CHATTERJEE , Gregory Frederick GROHOSKI , Kin Hing LEUNG , Dawei HUANG , Manoj UNNIKRISHNAN , Martin Russell RAUMANN , Bandish B. SHAH
摘要： The technology disclosed relates to runtime execution of configuration files on reconfigurable processors with varying configuration granularity. In particular, the technology disclosed relates to a runtime logic that is configured to receive a set of configuration files for an application, and load and execute a first subset of configuration files in the set of configuration files and associated application data on a first reconfigurable processor. The first reconfigurable processor has a first level of configurable granularity. The runtime logic is further configured to load and execute a second subset of configuration files in the set of configuration files and associated application data on a second reconfigurable processor. The second reconfigurable processor has a second level of configurable granularity that is different from the first level of configurable granularity.
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公开(公告)号：US20220197713A1
公开(公告)日：2022-06-23
申请号：US17522694
申请日：2021-11-09
发明人： Ram SIVARAMAKRISHNAN , Sumti JAIRATH , Emre Ali BURHAN , Manish K. SHAH , Raghu PRABHAKAR , Ravinder KUMAR , Arnav GOEL , Ranen CHATTERJEE , Gregory Frederick GROHOSKI , Kin Hing LEUNG , Dawei HUANG , Manoj UNNIKRISHNAN , Martin Russell RAUMANN , Bandish B. SHAH
摘要： The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.
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公开(公告)号：US20220197710A1
公开(公告)日：2022-06-23
申请号：US17522658
申请日：2021-11-09
发明人： Ram SIVARAMAKRISHNAN , Sumti JAIRATH , Emre Ali BURHAN , Manish K. SHAH , Raghu PRABHAKAR , Ravinder KUMAR , Arnav GOEL , Ranen CHATTERJEE , Gregory Frederick GROHOSKI , Kin Hing LEUNG , Dawei HUANG , Manoj UNNIKRISHNAN , Martin Russell RAUMANN , Bandish B. SHAH
摘要： The technology disclosed relates to inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and process application data for applications using a first reconfigurable processor and a second reconfigurable processor. The execution includes streaming configuration data in the configuration files and the application data between the first reconfigurable processor and the second reconfigurable processor using one or more SmartNIC buffers.
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