公开(公告)号：US20240330184A1

公开(公告)日：2024-10-03

申请号：US18542273

申请日：2023-12-15

Applicant: NetApp, Inc.

Inventor： Dipankar Roy

IPC: G06F12/0813

CPC classification number: G06F12/0813

Abstract: A method, computing device, and non-transitory machine-readable medium for performing asynchronous write-backs. Data is written to a cache file in a cache. The cache corresponds to a volume. A tracking metafile is updated based on the data written to the cache file. A record in the tracking metafile is determined to be full. The record corresponds to a group of blocks in the cache file. A write-back of data stored in the group of blocks in the cache file that corresponds to the record to the volume is initiated. The write-back is determined to have been completed. The tracking metafile us updated to indicate that the write-back has been completed.

公开(公告)号：US12086066B1

公开(公告)日：2024-09-10

申请号：US18184536

申请日：2023-03-15

Applicant: Cornami, Inc.

Inventor： Martin Alan Franz, II

IPC: G06F12/0813

CPC classification number: G06F12/0813 ,  G06F2212/1041

Abstract: A cache architecture for an array of identical cores arranged in a grid. Each of the cores include interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit. A first core of the array is configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation. A second core of the array is configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory. A third core of the array is configured as the cache memory. The memory of the third core is used as the cache memory. An address of the requested data from the cache index is passed to the third core to output the requested data.

公开(公告)号：US12019552B2

公开(公告)日：2024-06-25

申请号：US18123908

申请日：2023-03-20

Applicant: Marvell Asia Pte, Ltd.

Inventor： Craig Barner ,  David Asher ,  Richard Kessler ,  Bradley Dobbie ,  Daniel Dever ,  Thomas F. Hummel ,  Isam Akkawi

IPC: G06F12/00 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/084 ,  G06F12/0813 ,  G06F12/0842 ,  G06F2212/154

Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

公开(公告)号：US20240184724A1

公开(公告)日：2024-06-06

申请号：US18436919

申请日：2024-02-08

Applicant: Lodestar Licensing Group, LLC

Inventor： Robert M. Walker ,  Dan Skinner ,  Todd A. Merritt ,  J. Thomas Pawlowski

IPC: G06F13/16 ,  G06F3/06 ,  G06F9/30 ,  G06F12/0813 ,  G06F13/40 ,  G06F15/78

CPC classification number: G06F13/1673 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F9/3001 ,  G06F9/30043 ,  G06F12/0813 ,  G06F13/4068 ,  G06F15/7821 ,  G06F3/067

Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

公开(公告)号：US12001383B2

公开(公告)日：2024-06-04

申请号：US17858493

申请日：2022-07-06

Applicant: Groq, Inc.

Inventor： Dennis Charles Abts

IPC: G06F15/80 ,  G06F12/02 ,  G06F12/0813 ,  G06N20/00

CPC classification number: G06F15/80 ,  G06F12/023 ,  G06F12/0813 ,  G06F2212/251 ,  G06F2212/454 ,  G06N20/00

Abstract: Embodiments are directed to a deterministic streaming system with one or more deterministic streaming processors each having an array of processing elements and a first deterministic memory coupled to the processing elements. The deterministic streaming system further includes a second deterministic memory with multiple data banks having a global memory address space, and a controller. The controller initiates retrieval of first data from the data banks of the second deterministic memory as a first plurality of streams, each stream of the first plurality of streams streaming toward a respective group of processing elements of the array of processing elements. The controller further initiates writing of second data to the data banks of the second deterministic memory as a second plurality of streams, each stream of the second plurality of streams streaming from the respective group of processing elements toward a respective data bank of the second deterministic memory.

公开(公告)号：US20240152385A1

公开(公告)日：2024-05-09

申请号：US18411763

申请日：2024-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/48 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

公开(公告)号：US11940917B2

公开(公告)日：2024-03-26

申请号：US17862709

申请日：2022-07-12

Applicant: Dell Products L.P.

Inventor： Boris Glimcher

IPC: G06F12/0817 ,  G06F12/0813 ,  G06F12/0891

CPC classification number: G06F12/0824 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0891

Abstract: Methods and systems for managing storage of data in a distributed system are disclosed. To manage storage of data in a distributed system, a data processing system may include a network interface controller (NIC). The network interface controller may present emulated storages that may be used for data storage. The emulated storage devices may utilize storage resources of storage devices. The storage devices may be remote to the NIC. To reduce communication bandwidth and/or use of resources of the storage devices, the NIC and/or NICs of other data processing systems may implemented a distributed cache for data stored in the storage devices. The NICs may implement a method of managing the distributed cache to maintain synchronization between the distributed cache and the data stored in the storage devices.

公开(公告)号：US20240095170A1

公开(公告)日：2024-03-21

申请号：US18509407

申请日：2023-11-15

Applicant: Aux Mode Inc.

Inventor： Adam Rumanek ,  Charles Sinsofsky

IPC: G06F12/0811 ,  G06F9/451 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/0855 ,  G06F16/215 ,  G06N20/00

CPC classification number: G06F12/0811 ,  G06F9/451 ,  G06F12/0813 ,  G06F12/0833 ,  G06F12/0859 ,  G06F16/215 ,  G06N20/00

Abstract: Multi-cache-based digital output generation is provided. A system receives data objects that include fields from a remote data source. The system sorts the data objects based on a field to generate a sorted data set. The system cleans the sorted data set to generate a clean data set based on a policy. The system receives a request for a type of digital output based on the data objects received from the data source and loads a portion of the clean data set to a first level cache. The system selects a machine learning model configured for the type of digital output, and loads a primary cache with a subset of fields stored in the first level cache selected based on the machine learning model. The system generates, based on the first level cache being complete, digital output corresponding to the type of digital output from data in the primary cache.

公开(公告)号：US11874774B2

公开(公告)日：2024-01-16

申请号：US17031834

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan ,  Joe Sargunaraj ,  Chintan S. Patel ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F12/0891 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F9/467 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0833

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

公开(公告)号：US20230409376A1

公开(公告)日：2023-12-21

申请号：US18456568

申请日：2023-08-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Naveen BHORIA ,  David Matthew THOMPSON ,  Neelima MURALIDHARAN

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855

CPC classification number: G06F9/467 ,  G06F9/4881 ,  G06F9/4498 ,  G06F11/3037 ,  G06F9/544 ,  G06F12/0811 ,  G06F9/3867 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F9/30098 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/30189 ,  G06F13/1668 ,  G06F9/30079 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F2212/621 ,  G06F2212/1044 ,  G06F2212/1016 ,  G06F12/0804

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.