Process control using digital twins

    公开(公告)号:US12118368B2

    公开(公告)日:2024-10-15

    申请号:US18510539

    申请日:2023-11-15

    Inventor: Kilian Grefen

    CPC classification number: G06F9/4498 G06F9/4494

    Abstract: The present invention aims at providing an approach to digital twin-based process control for efficient and accurate achievement of process objectives. Heretofore, a controller service module (18) runs an event-driven control process in a digital twin domain for control of process entities operated in a process domain. The behavior of process entities is modeled through execution of state machine models. Event data is communicated asynchronously to the controller service module (18) for storage in a process cycle buffer (26). A model-based process controller (24) reads input information in processing cycles and controls process entities by operating state machine models to reflect the input of event data. It is checked whether the operation of state machine models triggers the generation of external control commands which are then output by an outbound interface (32) to process entities for control processing.

    METHOD FOR SHARING A STORAGE DEVICE AMONG MULTIPLE PROCESSORS AND ASSOCIATED ELECTRONIC DEVICE

    公开(公告)号:US20240211415A1

    公开(公告)日:2024-06-27

    申请号:US18534765

    申请日:2023-12-11

    CPC classification number: G06F13/1663 G06F9/4498 G06F13/1668

    Abstract: A method for sharing a storage device among multiple processors and an associated electronic device are provided. The method includes: controlling a first processor and a second processor to operate in an access mode and a detection mode, respectively; in response to the first processor operating in the access mode, utilizing the first processor to control a logic value of a busy signal, to indicate that the first processor has permission to access the storage device; in response to a first predetermined condition, controlling the first processor to enter the detection mode from the access mode; in response to a second predetermined condition, controlling the second processor to enter the access mode from the detection mode; and in response to the second processor operating in the access mode, utilizing the second processor to control the logic value of the busy signal, to indicate that the second processor has the permission.

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