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公开(公告)号：US20230185720A1
公开(公告)日：2023-06-15
申请号：US18107962
申请日：2023-02-09
发明人： Richard E. Kessler , David Asher , Shubhendu S. Mukherjee , Wilson P. Snyder, II , David Carlson , Jason Zebchuk , Isam Akkawi
IPC分类号： G06F12/0844 , G06F12/0813
CPC分类号： G06F12/0844 , G06F2212/1016 , G06F2212/608 , G06F12/0813
摘要： A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
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公开(公告)号：US12019552B2
公开(公告)日：2024-06-25
申请号：US18123908
申请日：2023-03-20
发明人： Craig Barner , David Asher , Richard Kessler , Bradley Dobbie , Daniel Dever , Thomas F. Hummel , Isam Akkawi
IPC分类号： G06F12/00 , G06F12/0813 , G06F12/084 , G06F12/0842
CPC分类号： G06F12/084 , G06F12/0813 , G06F12/0842 , G06F2212/154
摘要： Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
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公开(公告)号：US12047419B2
公开(公告)日：2024-07-23
申请号：US16854813
申请日：2020-04-21
IPC分类号： H04L41/28 , G06F21/57 , H04L9/40 , H04L41/0813
CPC分类号： H04L63/20 , G06F21/575 , H04L41/0813 , H04L41/28
摘要： The systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.
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公开(公告)号：US11615027B2
公开(公告)日：2023-03-28
申请号：US17530330
申请日：2021-11-18
发明人： Richard E. Kessler , David Asher , Shubhendu S. Mukherjee , Wilson P. Snyder, II , David Carlson , Jason Zebchuk , Isam Akkawi
IPC分类号： G06F12/0844 , G06F12/0813
摘要： A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
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公开(公告)号：US11188466B2
公开(公告)日：2021-11-30
申请号：US16788172
申请日：2020-02-11
发明人： Richard E. Kessler , David Asher , Shubhendu S. Mukherjee , Wilson P. Snyder, II , David Carlson , Jason Zebchuk , Isam Akkawi
IPC分类号： G06F12/08 , G06F12/0844 , G06F12/0813
摘要： A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
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公开(公告)号：US11868262B2
公开(公告)日：2024-01-09
申请号：US18107962
申请日：2023-02-09
发明人： Richard E. Kessler , David Asher , Shubhendu S Mukherjee , Wilson P. Snyder, II , David Carlson , Jason Zebchuk , Isam Akkawi
IPC分类号： G06F12/0844 , G06F12/0813
CPC分类号： G06F12/0844 , G06F12/0813 , G06F2212/1016 , G06F2212/608
摘要： A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.
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公开(公告)号：US11620223B2
公开(公告)日：2023-04-04
申请号：US17400959
申请日：2021-08-12
发明人： Craig Barner , David Asher , Richard Kessler , Bradley Dobbie , Daniel Dever , Thomas F. Hummel , Isam Akkawi
IPC分类号： G06F12/00 , G06F12/084 , G06F12/0842 , G06F12/0813
摘要： Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
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公开(公告)号：US20200252434A1
公开(公告)日：2020-08-06
申请号：US16854813
申请日：2020-04-21
摘要： A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.
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