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公开(公告)号：US11620223B2
公开(公告)日：2023-04-04
申请号：US17400959
申请日：2021-08-12
发明人： Craig Barner , David Asher , Richard Kessler , Bradley Dobbie , Daniel Dever , Thomas F. Hummel , Isam Akkawi
IPC分类号： G06F12/00 , G06F12/084 , G06F12/0842 , G06F12/0813
摘要： Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
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公开(公告)号：US12019552B2
公开(公告)日：2024-06-25
申请号：US18123908
申请日：2023-03-20
发明人： Craig Barner , David Asher , Richard Kessler , Bradley Dobbie , Daniel Dever , Thomas F. Hummel , Isam Akkawi
IPC分类号： G06F12/00 , G06F12/0813 , G06F12/084 , G06F12/0842
CPC分类号： G06F12/084 , G06F12/0813 , G06F12/0842 , G06F2212/154
摘要： Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
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