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公开(公告)号：US11379379B1
公开(公告)日：2022-07-05
申请号：US16862705
申请日：2020-04-30
IPC分类号： G06F12/121 , G06F12/0862
摘要： Described is a computing system and method for differential cache block sizing for computing systems. The method for differential cache block sizing includes determining, upon a cache miss at a cache, a number of available cache blocks given a payload length of the main memory and a cache block size for the last level cache, generating a main memory request including at least one indicator for a missed cache block and any available cache blocks, sending the main memory request to the main memory to obtain data associated with the missed cache block and each of the any available cache blocks, storing the data received for the missed cache block in the cache; and storing the data received for each of the any available cache blocks in the cache depending on a cache replacement algorithm.
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公开(公告)号：US11379368B1
公开(公告)日：2022-07-05
申请号：US17081151
申请日：2020-10-27
IPC分类号： G06F12/08 , G06F12/0802 , G06F9/50
摘要： An apparatus includes a plurality of processor cores; a shared cache connected to the plurality of processor cores; a cache control unit connected to the shared cache; and a way allocation circuitry connected to at least one of the plurality of processor cores. The way allocation circuitry is external to the plurality of processor cores. The cache control unit and the way allocation circuitry are cooperatively configured to process an intercepted memory request with respect to designated ways in the shared cache, the designated ways being based on a partition identifier and a partition table.
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公开(公告)号：US11620223B2
公开(公告)日：2023-04-04
申请号：US17400959
申请日：2021-08-12
发明人： Craig Barner , David Asher , Richard Kessler , Bradley Dobbie , Daniel Dever , Thomas F. Hummel , Isam Akkawi
IPC分类号： G06F12/00 , G06F12/084 , G06F12/0842 , G06F12/0813
摘要： Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
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公开(公告)号：US12019552B2
公开(公告)日：2024-06-25
申请号：US18123908
申请日：2023-03-20
发明人： Craig Barner , David Asher , Richard Kessler , Bradley Dobbie , Daniel Dever , Thomas F. Hummel , Isam Akkawi
IPC分类号： G06F12/00 , G06F12/0813 , G06F12/084 , G06F12/0842
CPC分类号： G06F12/084 , G06F12/0813 , G06F12/0842 , G06F2212/154
摘要： Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
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公开(公告)号：US11036643B1
公开(公告)日：2021-06-15
申请号：US16425462
申请日：2019-05-29
IPC分类号： G06F12/0891 , G06F12/0897 , G06F12/0811 , G06F12/0846
摘要： A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
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