知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.018 秒)

    Efficient inclusive cache management
    5.
    发明授权
    Efficient inclusive cache management 有权

    公开(公告)号：US10901902B2

    公开(公告)日：2021-01-26

    申请号：US16360254

    申请日：2019-03-21

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chad G. Wilson ,  Robert J Sonnelitter, III ,  Tim Bronson ,  Ekaterina M. Ambroladze ,  Hieu T Huynh ,  Jason D Kohl ,  Chakrapani Rayadurgam

    IPC分类号： G06F12/10 ,  G06F12/084

    摘要： Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.

    Preinstall of partial store cache lines
    6.
    发明授权
    Preinstall of partial store cache lines 有权

    公开(公告)号：US10529396B2

    公开(公告)日：2020-01-07

    申请号：US15629923

    申请日：2017-06-22

    申请人： International Business Machines Corporation

    发明人： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

    IPC分类号： G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C8/06

    摘要： A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

    EFFICIENT INCLUSIVE CACHE MANAGEMENT
    8.
    发明申请
    EFFICIENT INCLUSIVE CACHE MANAGEMENT 审中-公开

    公开(公告)号：US20200301831A1

    公开(公告)日：2020-09-24

    申请号：US16360254

    申请日：2019-03-21

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chad G. Wilson ,  Robert J Sonnelitter, III ,  Tim Bronson ,  Ekaterina M. Ambroladze ,  Hieu T Huynh ,  Jason D Kohl ,  Chakrapani Rayadurgam

    IPC分类号： G06F12/084

    摘要： Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.

    COHERENCY MAINTENANCE VIA PHYSICAL CACHE COORDINATE COMPARISON
    9.
    发明申请
    COHERENCY MAINTENANCE VIA PHYSICAL CACHE COORDINATE COMPARISON 审中-公开

    公开(公告)号：US20200293448A1

    公开(公告)日：2020-09-17

    申请号：US16299287

    申请日：2019-03-12

    申请人： International Business Machines Corporation

    发明人： Kevin Lopes ,  Deanna P. D. Berger ,  Chad G. Wilson

    IPC分类号： G06F12/0811 ,  G06F12/0817 ,  G06F12/0875

    摘要： Utilizing physical cache address comparison for maintaining coherency. Operations are performed on data in lines of a cache of the computing system and virtual addresses are loaded into a cache controller. The virtual addresses correspond with lines associated with performing the operations. A physical address of a line is determined in response to having performed a first cache directory lookup of the line. The physical address from the first operation is compared with other physical addresses associated with other operations to determine whether the other operations utilize the same physical address as the first operation. In response to matching physical locations, determinations are made as to whether a conflict exists in the data at the physical addresses that match. Thus, the coherency maintenance is free from looking up virtual addresses to determine whether the line of the cache includes incoherent data.

    PREINSTALL OF PARTIAL STORE CACHE LINES
    10.
    发明申请
    PREINSTALL OF PARTIAL STORE CACHE LINES 审中-公开

    公开(公告)号：US20180374522A1

    公开(公告)日：2018-12-27

    申请号：US15629923

    申请日：2017-06-22

    申请人： International Business Machines Corporation

    发明人： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

    IPC分类号： G11C8/06 ,  G06F3/06 ,  G06F13/16

    摘要： A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.