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公开(公告)号：US20230318979A1
公开(公告)日：2023-10-05
申请号：US17708073
申请日：2022-03-30
发明人： Avery Francois , Kenneth Douglas Klapproth , Guy G. Tracy , Matthias Klein , Gregory William Alexander
IPC分类号： H04L47/10 , H04L45/122
CPC分类号： H04L47/13 , H04L45/122
摘要： Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving a command for execution and based at least in part on a determination that the clockwise ring network and the counterclockwise ring network are both available for transmission, performing a bidirectional execution of the command. The bidirectional execution includes transmitting a first warning signal on the clockwise ring network and a second warning signal on the counterclockwise ring network, transmitting the command on the clockwise ring network a first number of clock cycles after the first warning signal, and transmitting the command on the counterclockwise ring network a second number of clock cycles after the second warning signal.
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公开(公告)号：US10884890B2
公开(公告)日：2021-01-05
申请号：US16532612
申请日：2019-08-06
发明人： Ram Sai Manoj Bamdhamravuri , Deanna Postles Dunn Berger , Mark R. Hodges , Kenneth D. Klapproth , Guy G. Tracy , Craig R. Walters
摘要： Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.
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公开(公告)号：US11782777B1
公开(公告)日：2023-10-10
申请号：US17808119
申请日：2022-06-22
发明人： Gregory William Alexander , Deanna Postles Dunn Berger , Timothy Bronson , Lior Binyamini , Richard Joseph Branciforte , Guy G. Tracy
CPC分类号： G06F11/0724 , G06F11/0757 , G06F11/202 , G06F11/1608
摘要： A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.
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公开(公告)号：US20180341422A1
公开(公告)日：2018-11-29
申请号：US15603728
申请日：2017-05-24
发明人： Deanna P. Berger , Michael A. Blake , Ashraf Elsharif , Kenneth D. Klapproth , Pak-kin Mak , Robert J. Sonnelitter, III , Guy G. Tracy
IPC分类号： G06F3/06 , G06F12/0893 , G06F12/0842
CPC分类号： G06F12/0842 , G06F12/0893 , G06F2212/62
摘要： An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.
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公开(公告)号：US20180336134A1
公开(公告)日：2018-11-22
申请号：US15598837
申请日：2017-05-18
发明人： Michael A. Blake , Timothy C. Bronson , Ashraf ElSharif , Kenneth D. Klapproth , Vesselina K. Papazova , Guy G. Tracy
IPC分类号： G06F12/0817 , G06F12/0891
CPC分类号： G06F12/0817 , G06F12/0891 , G06F2212/1024 , G06F2212/60 , G06F2212/621
摘要： Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.
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6.发明申请公开(公告)号：US20180307628A1
公开(公告)日：2018-10-25
申请号：US15496525
申请日：2017-04-25
发明人： Michael A. Blake , Pak-kin Mak , Robert J. Sonnelitter, III , Timothy W. Steele , Gary E. Strait , Poornima P. Sulibele , Guy G. Tracy
IPC分类号： G06F12/14 , G06F12/0891 , G06F13/40
CPC分类号： G06F12/1466 , G06F12/0891 , G06F13/4036 , G06F2212/1052
摘要： A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.
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公开(公告)号：US10540251B2
公开(公告)日：2020-01-21
申请号：US15601272
申请日：2017-05-22
发明人： Ram Sai Manoj Bamdhamravuri , Deanna Postles Dunn Berger , Mark R. Hodges , Kenneth D. Klapproth , Guy G. Tracy , Craig R. Walters
摘要： Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.
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公开(公告)号：US10331576B2
公开(公告)日：2019-06-25
申请号：US15496525
申请日：2017-04-25
发明人： Michael A. Blake , Pak-kin Mak , Robert J. Sonnelitter, III , Timothy W. Steele , Gary E. Strait , Poornima P. Sulibele , Guy G. Tracy
IPC分类号： G06F12/14 , G06F12/0891 , G06F13/40
摘要： A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.
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公开(公告)号：US20190179765A1
公开(公告)日：2019-06-13
申请号：US16281132
申请日：2019-02-21
发明人： Ekaterina M. Ambroladze , Deanna P. D. Berger , Michael A. Blake , Pak-kin Mak , Robert J. Sonnelitter, III , Guy G. Tracy , Chad G. Wilson
IPC分类号： G06F12/0891 , G06F12/0897 , G06F12/0804 , G06F12/0864
摘要： In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.
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公开(公告)号：US10055355B1
公开(公告)日：2018-08-21
申请号：US15716713
申请日：2017-09-27
发明人： Ekaterina M. Ambroladze , Deanna P. D. Berger , Michael A. Blake , Pak-Kin Mak , Robert J. Sonnelitter, III , Guy G. Tracy , Chad G. Wilson
IPC分类号： G06F12/08 , G06F12/0891 , G06F12/0804
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0864 , G06F12/0897 , G06F2212/1024 , G06F2212/60
摘要： In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.
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