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    SYSTEM FOR COLLABORATIVE HARDWARE RTL LOGIC TIMING DEBUG IN INTEGRATED CIRCUIT DESIGNS
    3.
    发明公开
    SYSTEM FOR COLLABORATIVE HARDWARE RTL LOGIC TIMING DEBUG IN INTEGRATED CIRCUIT DESIGNS 审中-公开

    公开(公告)号：US20230214564A1

    公开(公告)日：2023-07-06

    申请号：US17567598

    申请日：2022-01-03

    申请人： International Business Machines Corporation

    发明人： Arun Joseph ,  Wolfgang Roesner ,  Shashidhar Reddy ,  SAMPATH GOUD BADDAM ,  Anthony Saporito ,  Matthias Klein

    IPC分类号： G06F30/327

    CPC分类号： G06F30/327 ,  G06F2119/12

    摘要： A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

    Handling an input/output store instruction
    6.
    发明授权
    Handling an input/output store instruction 有权

    公开(公告)号：US11593107B2

    公开(公告)日：2023-02-28

    申请号：US17351647

    申请日：2021-06-18

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Brenton Belmar ,  Peter Dana Driever

    IPC分类号： G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/07 ,  G06F11/14

    摘要： An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION
    7.
    发明申请
    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION 有权

    公开(公告)号：US20210311891A1

    公开(公告)日：2021-10-07

    申请号：US17354302

    申请日：2021-06-22

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Christoph Raisch ,  Marco Kraemer ,  Frank Siegfried Lehnert ,  Matthias Klein ,  Jonathan D. Bradbury ,  Christian Jacobi ,  Peter Dana Driever ,  Brenton Belmar

    IPC分类号： G06F13/16 ,  G06F9/30

    摘要： An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

    Instant quiescing of an accelerator
    8.
    发明授权
    Instant quiescing of an accelerator 有权

    公开(公告)号：US11119928B2

    公开(公告)日：2021-09-14

    申请号：US16286861

    申请日：2019-02-27

    申请人： International Business Machines Corporation

    发明人： Matthias Klein ,  Ashutosh Misra ,  Girish Gopala Kurup

    IPC分类号： G06F12/08 ,  G06F12/0831 ,  G06F13/28 ,  G06F9/38

    摘要： A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.

    Efficient generation of instrumentation data for direct memory access operations
    9.
    发明授权
    Efficient generation of instrumentation data for direct memory access operations 有权

    公开(公告)号：US11099966B2

    公开(公告)日：2021-08-24

    申请号：US16738311

    申请日：2020-01-09

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Matthias Klein ,  Deanna P. D. Berger ,  Craig R. Walters

    IPC分类号： G06F11/34 ,  G06F11/30 ,  G06F13/28

    摘要： Aspects of the invention include efficient generation of instrumentation data for direct memory access operations. A non-limiting example apparatus includes an instrumentation component, residing in a cache in communication with a plurality of processing units, an accelerator, and a plurality of input output interfaces. The cache includes a direct memory access monitor that receives events from the accelerator its respective I/O interface and stores DMA state and latency for each event. The cache also includes a bucket including a DMA counter and a latency counter in communication with the DMA monitor, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.

    EXTENDED ASYNCHRONOUS DATA MOVER FUNCTIONS COMPATIBILITY INDICATION
    10.
    发明申请
    EXTENDED ASYNCHRONOUS DATA MOVER FUNCTIONS COMPATIBILITY INDICATION 有权

    公开(公告)号：US20210224073A1

    公开(公告)日：2021-07-22

    申请号：US17224198

    申请日：2021-04-07

    申请人： International Business Machines Corporation

    发明人： Louis P. Gomes ,  Bruce Giamei ,  Timothy Slegel ,  Mark Farrell ,  Matthias Klein

    IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30

    摘要： A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.