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公开(公告)号：US11953982B2
公开(公告)日：2024-04-09
申请号：US17813341
申请日：2022-07-19
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Alejandro Alberto Cook Lobo , Andrew A. Turner , Christian Jacobi , Eberhard Engler , Edward C. McCain , Kevin P. Low , Phillip John Restle , Pradeep Bhadravati Parashurama , Tobias Webel , Alper Buyuktosunoglu , Karl Evan Smock Anderson , Sean Michael Carey , Kennedy Cheruiyot , Daniel Kiss , Isidore G. Bendrihem , Ian Krispin Carmichael
CPC classification number: G06F11/0793 , G06F1/305 , G06F11/0721 , G06F11/076
Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.
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公开(公告)号：US11907074B2
公开(公告)日：2024-02-20
申请号：US17484415
申请日：2021-09-24
Applicant: International Business Machines Corporation
Inventor： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Michael B. Spear
CPC classification number: G06F11/1423 , G06F5/06 , G06F11/0745 , G06F13/28 , G06F13/385
Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.
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公开(公告)号：US20230401161A1
公开(公告)日：2023-12-14
申请号：US18452310
申请日：2023-08-18
Applicant: International Business Machines Corporation
Inventor： Markus Helms , Christian Jacobi , Ulrich Mayer , Martin Recktenwald , Johannes C. Reichart , Anthony Saporito , Aaron Tsai
IPC: G06F12/1045 , G06F12/0864 , G06F12/0842 , G06F12/0808 , G06F12/0817 , G06F12/1009
CPC classification number: G06F12/1063 , G06F12/0864 , G06F12/0842 , G06F12/0808 , G06F12/0817 , G06F12/1009 , G06F2212/656 , G06F12/0897
Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.
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公开(公告)号：US20230315631A1
公开(公告)日：2023-10-05
申请号：US17709807
申请日：2022-03-31
Applicant: International Business Machines Corporation
Inventor： Yair Fried , Aaron Tsai , Eyal Naor , Christian Jacobi , Timothy Bronson , Chung-Lung K. Shum
IPC: G06F12/0811
CPC classification number: G06F12/0811 , G06F2212/311
Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.
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公开(公告)号：US11675513B2
公开(公告)日：2023-06-13
申请号：US17403617
申请日：2021-08-16
Applicant: International Business Machines Corporation
Inventor： Scott B. Compton , Jeffrey Richard Suarez , Matthew Michael Garcia Pardini , Christian Jacobi , Dominik Steenken , Sri Hari Kolusu , Vicky Vezinaw
IPC: G06F3/06
CPC classification number: G06F3/0643 , G06F3/0613 , G06F3/0685
Abstract: A computer-implemented method, according to one embodiment, includes: storing records in an input data buffer, where each of the records include a key which is appended to payload data in the respective record. Moreover, for each of the records: shearing the key associated with the record from the payload data, normalizing the sheared key, and storing the normalized sheared key in a first target area of memory. A determination is made as to whether a size of the payload data in the record is outside a predetermine range, and in response to determining that the size of the payload data in the record is outside the predetermine range, the payload data is stored in a second target area of memory. A data locator is also appended to the normalized sheared key in the first target area of memory to form a sheared record.
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Patent Agency Ranking
公开(公告)号：US11656871B2
公开(公告)日：2023-05-23
申请号：US17480337
申请日：2021-09-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Christoph Raisch , Marco Kraemer , Frank Siegfried Lehnert , Matthias Klein , Jonathan D. Bradbury , Christian Jacobi , Brenton Belmar , Peter Dana Driever
CPC classification number: G06F9/30043 , G06F9/30145 , G06F9/3871 , G06F9/4411 , G06F9/451 , G06F9/544 , G06F9/546 , G06F11/0772
Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.
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公开(公告)号：US20230115533A1
公开(公告)日：2023-04-13
申请号：US17484415
申请日：2021-09-24
Applicant: International Business Machines Corporation
Inventor： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Michael B. Spear
Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.
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公开(公告)号：US11593107B2
公开(公告)日：2023-02-28
申请号：US17351647
申请日：2021-06-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Christoph Raisch , Marco Kraemer , Frank Siegfried Lehnert , Matthias Klein , Jonathan D. Bradbury , Christian Jacobi , Brenton Belmar , Peter Dana Driever
Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.
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公开(公告)号：US11586542B2
公开(公告)日：2023-02-21
申请号：US17226592
申请日：2021-04-09
Applicant: International Business Machines Corporation
Inventor： Christian Zoellin , Christian Jacobi , Chung-Lung K. Shum , Martin Recktenwald , Anthony Saporito , Aaron Tsai
IPC: G06F12/0817 , G06F12/0831 , G06F12/0842
Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.
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公开(公告)号：US11182293B2
公开(公告)日：2021-11-23
申请号：US16704021
申请日：2019-12-05
Applicant: International Business Machines Corporation
Inventor： Simon H. Friedmann , Christian Jacobi , Markus Kaltenbach , Ulrich Mayer , Anthony Saporito
IPC: G06F12/10 , G06F12/0811 , G06F12/0855 , G06F12/0864
Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.
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