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公开(公告)号：US11144321B2
公开(公告)日：2021-10-12
申请号：US16280285
申请日：2019-02-20
Applicant: International Business Machines Corporation
Inventor： Yair Fried , Jonathan Hsieh , Eyal Naor , James Bonanno , Gregory William Alexander
Abstract: Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.
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公开(公告)号：US10929142B2
公开(公告)日：2021-02-23
申请号：US16358791
申请日：2019-03-20
Applicant: International Business Machines Corporation
Inventor： Gregory William Alexander , James Bonanno , Adam Collura , James Raymond Cuffney , Yair Fried , Jonathan Hsieh , Jang-Soo Lee , Edward Malley , Anthony Saporito , Eyal Naor
Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.
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公开(公告)号：US20190018773A1
公开(公告)日：2019-01-17
申请号：US15813751
申请日：2017-11-15
Applicant: International Business Machines Corporation
Inventor： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC: G06F12/0817 , G06F12/0811 , G06F9/46
CPC classification number: G06F12/0828 , G06F9/467 , G06F12/0811 , G06F2212/60 , G06F2212/621
Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
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公开(公告)号：US20190018681A1
公开(公告)日：2019-01-17
申请号：US15647649
申请日：2017-07-12
Applicant: International Business Machines Corporation
Inventor： Eyal Naor , Martin Recktenwald , Christian Zoellin , Aaron Tsai
CPC classification number: G06F9/30032 , G06F9/226
Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
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公开(公告)号：US10956328B2
公开(公告)日：2021-03-23
申请号：US16436159
申请日：2019-06-10
Applicant: International Business Machines Corporation
Inventor： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC: G06F12/00 , G06F12/0817 , G06F9/46 , G06F12/0811
Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
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Patent Agency Ranking
公开(公告)号：US10409724B2
公开(公告)日：2019-09-10
申请号：US15813751
申请日：2017-11-15
Applicant: International Business Machines Corporation
Inventor： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC: G06F12/00 , G06F12/0817 , G06F9/46 , G06F12/0811
Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
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公开(公告)号：US10353707B2
公开(公告)日：2019-07-16
申请号：US15647649
申请日：2017-07-12
Applicant: International Business Machines Corporation
Inventor： Eyal Naor , Martin Recktenwald , Christian Zoellin , Aaron Tsai
Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
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公开(公告)号：US20190213129A1
公开(公告)日：2019-07-11
申请号：US16358438
申请日：2019-03-19
Applicant: International Business Machines Corporation
Inventor： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC: G06F12/0817 , G06F12/0811 , G06F9/46
CPC classification number: G06F12/0828 , G06F9/467 , G06F12/0811 , G06F2212/60 , G06F2212/621
Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
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公开(公告)号：US20190018772A1
公开(公告)日：2019-01-17
申请号：US15649186
申请日：2017-07-13
Applicant: International Business Machines Corporation
Inventor： Willm Hinrichs , Markus Kaltenbach , Eyal Naor , Martin Recktenwald
IPC: G06F12/0817 , G06F12/0811 , G06F9/46
CPC classification number: G06F12/0828 , G06F9/467 , G06F12/0811 , G06F2212/60 , G06F2212/621
Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
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公开(公告)号：US20180232292A1
公开(公告)日：2018-08-16
申请号：US15432584
申请日：2017-02-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Erez Barak , Oz D. Hershkovitz , Gilad Merran , Eyal Naor
CPC classification number: G06F11/26 , G06F11/2236 , G06F17/5022 , G06F2217/68
Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
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