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    Temporary pipeline marking for processor error workarounds
    2.
    发明授权
    Temporary pipeline marking for processor error workarounds 有权
    处理器错误解决方法的临时管道标记

    公开(公告)号：US09575836B2

    公开(公告)日：2017-02-21

    申请号：US15251316

    申请日：2016-08-30

    Applicant: International Business Machines Corporation

    Inventor： Erez Barak ,  Steven R. Carlough ,  Eyal Gonen ,  Juergen Haess ,  Silvia M. Mueller

    IPC: G06F11/00 ,  G06F11/14 ,  G06F9/38

    CPC classification number: G06F11/142 ,  G06F9/3867 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/2028 ,  G06F11/3024 ,  G06F11/3466 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/85 ,  G06F2201/86

    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.

    Abstract translation: 实施例包括用于处理器错误解决方案的临时管道标记的计算机系统，该计算机系统具有被配置为执行方法的处理器。 该方法包括监视处理器的流水线，用于预定的事件，以使处理器处于由于卡住状态或重复的资源争用导致性能下降而导致错误指令执行结果的卡住状态。 管道被标记为基于检测事件的解决方法操作。 基于管道的标记触发清除动作。 基于触发清除动作，管道的标记被清除。

    CHECKING A COMPUTER PROCESSOR DESIGN FOR SOFT ERROR HANDLING
    4.
    发明申请
    CHECKING A COMPUTER PROCESSOR DESIGN FOR SOFT ERROR HANDLING 审中-公开

    公开(公告)号：US20180260311A1

    公开(公告)日：2018-09-13

    申请号：US15810548

    申请日：2017-11-13

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Erez Barak ,  Nicol Hofmann ,  Cédric Lichtenau ,  Osher Yifrach

    IPC: G06F11/36 ,  G06F17/50

    CPC classification number: G06F11/3684 ,  G06F11/3672 ,  G06F11/3688 ,  G06F11/3692 ,  G06F17/5009

    Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.

    CHECKING A COMPUTER PROCESSOR DESIGN FOR SOFT ERROR HANDLING
    5.
    发明申请
    CHECKING A COMPUTER PROCESSOR DESIGN FOR SOFT ERROR HANDLING 审中-公开

    公开(公告)号：US20180260308A1

    公开(公告)日：2018-09-13

    申请号：US15453311

    申请日：2017-03-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Erez Barak ,  Nicol Hofmann ,  Cédric Lichtenau ,  Osher Yifrach

    IPC: G06F11/36 ,  G06F17/50

    CPC classification number: G06F11/3684 ,  G06F11/3672 ,  G06F11/3688 ,  G06F11/3692 ,  G06F17/5009

    Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.

    Modified design debugging using differential trace back
    8.
    发明授权
    Modified design debugging using differential trace back 有权

    公开(公告)号：US10572624B2

    公开(公告)日：2020-02-25

    申请号：US15966072

    申请日：2018-04-30

    Applicant: International Business Machines Corporation

    Inventor： Erez Barak ,  Shlomit Koyfman ,  Eyal Naor ,  Ziv Nevo ,  Osher Yifrach

    IPC: G06F17/50

    Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.

    Error checking of a multi-threaded computer processor design under test
    9.
    发明授权
    Error checking of a multi-threaded computer processor design under test 有权

    公开(公告)号：US10324815B2

    公开(公告)日：2019-06-18

    申请号：US15432584

    申请日：2017-02-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Erez Barak ,  Oz D. Hershkovitz ,  Gilad Merran ,  Eyal Naor

    IPC: G06F11/00 ,  G06F11/26 ,  G06F11/22 ,  G06F17/50

    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.

    Reducing clock power consumption of a computer processor
    10.
    发明授权
    Reducing clock power consumption of a computer processor 有权

    公开(公告)号：US10296687B2

    公开(公告)日：2019-05-21

    申请号：US15903697

    申请日：2018-02-23

    Applicant: International Business Machines Corporation

    Inventor： Erez Barak ,  Giora Biran ,  Amir Turi ,  Osher Yifrach

    IPC: G06F17/50

    Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

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