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公开(公告)号：US12038841B2
公开(公告)日：2024-07-16
申请号：US17713264
申请日：2022-04-05
发明人： Tu-An T. Nguyen , Matthias Klein , Gregory William Alexander , Jason D. Kohl , Winston Herring , Timothy Bronson , Christian Jacobi
IPC分类号： G06F12/08 , G06F9/34 , G06F9/38 , G06F12/0815 , G06F12/084 , G06F12/0897
CPC分类号： G06F12/084 , G06F9/34 , G06F9/3816 , G06F12/0815 , G06F12/0897
摘要： Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.
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公开(公告)号：US11880304B2
公开(公告)日：2024-01-23
申请号：US17664722
申请日：2022-05-24
发明人： Taylor J Pritchard , Aaron Tsai , Richard Joseph Branciforte , Ashraf ElSharif , Gregory William Alexander , Deanna Postles Dunn Berger , Michael Fee
IPC分类号： G06F12/0811
CPC分类号： G06F12/0811 , G06F2212/1021
摘要： To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.
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公开(公告)号：US20230385195A1
公开(公告)日：2023-11-30
申请号：US17664722
申请日：2022-05-24
发明人： Taylor J. Pritchard , Aaron Tsai , Richard Joseph Branciforte , Ashraf ElSharif , Gregory William Alexander , Deanna Postles Dunn Berger , Michael Fee
IPC分类号： G06F12/0811
CPC分类号： G06F12/0811 , G06F2212/1021
摘要： To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.
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公开(公告)号：US11782777B1
公开(公告)日：2023-10-10
申请号：US17808119
申请日：2022-06-22
发明人： Gregory William Alexander , Deanna Postles Dunn Berger , Timothy Bronson , Lior Binyamini , Richard Joseph Branciforte , Guy G. Tracy
CPC分类号： G06F11/0724 , G06F11/0757 , G06F11/202 , G06F11/1608
摘要： A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.
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公开(公告)号：US11782836B1
公开(公告)日：2023-10-10
申请号：US17657169
申请日：2022-03-30
发明人： Jason D Kohl , Winston Herring , Tu-An T. Nguyen , Gregory William Alexander , Timothy Bronson , Christian Jacobi
IPC分类号： G06F12/084 , G06F9/38 , G06F12/0815
CPC分类号： G06F12/084 , G06F9/3834 , G06F12/0815
摘要： A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.
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公开(公告)号：US20230318979A1
公开(公告)日：2023-10-05
申请号：US17708073
申请日：2022-03-30
发明人： Avery Francois , Kenneth Douglas Klapproth , Guy G. Tracy , Matthias Klein , Gregory William Alexander
IPC分类号： H04L47/10 , H04L45/122
CPC分类号： H04L47/13 , H04L45/122
摘要： Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving a command for execution and based at least in part on a determination that the clockwise ring network and the counterclockwise ring network are both available for transmission, performing a bidirectional execution of the command. The bidirectional execution includes transmitting a first warning signal on the clockwise ring network and a second warning signal on the counterclockwise ring network, transmitting the command on the clockwise ring network a first number of clock cycles after the first warning signal, and transmitting the command on the counterclockwise ring network a second number of clock cycles after the second warning signal.
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公开(公告)号：US20230281132A1
公开(公告)日：2023-09-07
申请号：US17686477
申请日：2022-03-04
发明人： Deanna Postles Dunn Berger , Gregory William Alexander , Richard Joseph Branciforte , Aaron Tsai , Markus Kaltenbach
IPC分类号： G06F12/0891 , G06F12/084 , G06F12/0837
CPC分类号： G06F12/0891 , G06F12/084 , G06F12/0837 , G06F2212/62
摘要： Embodiments are for special tracking pool enhancement for core L1 address invalidates. An invalidate request is designated to fill an entry in a queue in a local cache of a processor core, the queue including a first allocation associated with processing any type of invalidate request and a second allocation associated with processing an invalidate request not requiring a response in order for a controller to be made available, the entry being in the second allocation. Responsive to designating the invalidate request to fill the entry in the queue in the local cache, a state of the controller that made the invalidate request is changed to available based at least in part on the entry being in the second allocation.
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公开(公告)号：US11620231B2
公开(公告)日：2023-04-04
申请号：US17407248
申请日：2021-08-20
发明人： Ram Sai Manoj Bamdhamravuri , Craig R. Walters , Christian Jacobi , Timothy Bronson , Gregory William Alexander , Hieu T. Huynh , Robert J. Sonnelitter, III , Jason D. Kohl , Deanna P. D. Berger , Richard Joseph Branciforte
IPC分类号： G06F12/08 , G06F12/0891 , G06F12/123 , G06F12/0895
摘要： Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.
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公开(公告)号：US11205005B2
公开(公告)日：2021-12-21
申请号：US16578739
申请日：2019-09-23
发明人： Matthew Michael Garcia Pardini , Gregory William Alexander , Jonathan Ting Hsieh , Michael P Mullen , Olaf Knute Hendrickson
摘要： A computer-implemented method for detecting vulnerabilities in microarchitectures. A non-limiting example of the computer-implemented method includes creating a simulation for execution on a model of a microarchitecture, the simulation including a set of instructions and a placeholder for holding a piece of secret data. The computer-implemented method executes the simulation a first time on the model of the microarchitecture with a first piece of secret data stored in the placeholder and stores a first output of the first executed simulation. The computer-implemented method executes the simulation a second time on the model of the microarchitecture with a second piece of secret data stored in the placeholder and stores a second output of the second executed simulation. The computer-implemented method compares the first output with the second output and provides an indication of a microarchitecture vulnerability when there is a difference between the first output and the second output.
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公开(公告)号：US20200285478A1
公开(公告)日：2020-09-10
申请号：US16292933
申请日：2019-03-05
摘要： A computer data processing system includes a plurality of logical registers, each including multiple storage sections. A processor writes data a storage section based on a dispatched first instruction, and sets a valid bit corresponding to the storage section that receives the data. In response to each subsequent instruction, the processor sets an evictor valid bit indicating a subsequent instruction has written new data to a storage section written by the first instruction, and updates the valid bit to indicate the storage section containing the new written data. A register combination unit generates a combined evictor tag to identify a most recent subsequent instruction. The processor determines the most recent subsequent instruction based on the combined evictor tag in response to a flush event, and unsets all the evictor tag valid bits set by the most the most recent subsequent instruction along with all previous subsequent instructions.
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