-
公开(公告)号：US20230418707A1
公开(公告)日：2023-12-28
申请号：US17808271
申请日：2022-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ram Sai Manoj Bamdhamravuri , Robert J. Sonnelitter, III , Ulrich Mayer , Chad G. Wilson , Avery Francois
CPC classification number: G06F11/106 , G06F11/1068 , G06F3/0673 , G06F3/0631 , G06F3/0644 , G06F3/0619
Abstract: A computer system and a method implementing a remote access array are provided. A first drawer may include a first processor chip. A first main memory region may be operatively connected to the first processor chip. A first non-addressable memory region may be operatively connected to the first processor chip and may include the first remote access array. The first remote access array may be configured to track data portions that are pulled from the first main memory region and that are sent to an external node. The first remote access array may be backed up in the first main memory region. The first remote access array may include one or more entries and may be configured to scrub all of the entries in response to a multi-drawer working partition being shrunk to fit within the first drawer.
-
公开(公告)号：US20180336116A1
公开(公告)日：2018-11-22
申请号：US15601272
申请日：2017-05-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ram Sai Manoj Bamdhamravuri , Deanna Postles Dunn Berger , Mark R. Hodges , Kenneth D. Klapproth , Guy G. Tracy , Craig R. Walters
Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.
-
Patent Agency Ranking
公开(公告)号：US11620231B2
公开(公告)日：2023-04-04
申请号：US17407248
申请日：2021-08-20
Applicant: International Business Machines Corporation
Inventor： Ram Sai Manoj Bamdhamravuri , Craig R. Walters , Christian Jacobi , Timothy Bronson , Gregory William Alexander , Hieu T. Huynh , Robert J. Sonnelitter, III , Jason D. Kohl , Deanna P. D. Berger , Richard Joseph Branciforte
IPC: G06F12/08 , G06F12/0891 , G06F12/123 , G06F12/0895
Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.
-
公开(公告)号：US10884890B2
公开(公告)日：2021-01-05
申请号：US16532612
申请日：2019-08-06
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ram Sai Manoj Bamdhamravuri , Deanna Postles Dunn Berger , Mark R. Hodges , Kenneth D. Klapproth , Guy G. Tracy , Craig R. Walters
Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.
-
公开(公告)号：US11947418B2
公开(公告)日：2024-04-02
申请号：US17808271
申请日：2022-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ram Sai Manoj Bamdhamravuri , Robert J Sonnelitter, III , Ulrich Mayer , Chad G. Wilson , Avery Francois
CPC classification number: G06F11/106 , G06F3/0619 , G06F3/0631 , G06F3/0644 , G06F3/0673 , G06F11/1068
Abstract: A computer system and a method implementing a remote access array are provided. A first drawer includes a first processor chip. A first main memory region is operatively connected to the first processor chip. A first non-addressable memory region is operatively connected to the first processor chip and includes the first remote access array. The first remote access array is configured to track data portions that are stored in the first main memory region and for which copies were created and sent to an external node. The first remote access array is backed up in the first main memory region. The first remote access array includes one or more entries and is configured to update all of the entries in response to a multi-drawer working partition being reduced to fit within the first drawer.
-
公开(公告)号：US11487672B1
公开(公告)日：2022-11-01
申请号：US17407228
申请日：2021-08-20
Applicant: International Business Machines Corporation
Inventor： Chunggeon Rhee , Craig R. Walters , Ram Sai Manoj Bamdhamravuri , Timothy Bronson , Gregory William Alexander
IPC: G06F12/0895 , G06F12/084 , G06F12/0891 , G06F12/0817
Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.
-
公开(公告)号：US10540251B2
公开(公告)日：2020-01-21
申请号：US15601272
申请日：2017-05-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ram Sai Manoj Bamdhamravuri , Deanna Postles Dunn Berger , Mark R. Hodges , Kenneth D. Klapproth , Guy G. Tracy , Craig R. Walters
Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.
-
-
-
-
-
-
Search Results
7
records
(took 0.014 seconds)
