公开(公告)号：US20230315629A1

公开(公告)日：2023-10-05

申请号：US17713267

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Vesselina Papazova

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

公开(公告)号：US12038841B2

公开(公告)日：2024-07-16

申请号：US17713264

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Winston Herring ,  Timothy Bronson ,  Christian Jacobi

IPC: G06F12/08 ,  G06F9/34 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F9/34 ,  G06F9/3816 ,  G06F12/0815 ,  G06F12/0897

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

公开(公告)号：US20190266305A1

公开(公告)日：2019-08-29

申请号：US16405467

申请日：2019-05-07

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F17/50

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

公开(公告)号：US11620231B2

公开(公告)日：2023-04-04

申请号：US17407248

申请日：2021-08-20

Applicant: International Business Machines Corporation

Inventor： Ram Sai Manoj Bamdhamravuri ,  Craig R. Walters ,  Christian Jacobi ,  Timothy Bronson ,  Gregory William Alexander ,  Hieu T. Huynh ,  Robert J. Sonnelitter, III ,  Jason D. Kohl ,  Deanna P. D. Berger ,  Richard Joseph Branciforte

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/123 ,  G06F12/0895

Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

公开(公告)号：US11048427B2

公开(公告)日：2021-06-29

申请号：US16280641

申请日：2019-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D. Kohl ,  Tim Bronson ,  Hieu T. Huynh ,  Michael Andrew Blake

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

公开(公告)号：US20180285277A1

公开(公告)日：2018-10-04

申请号：US15472610

申请日：2017-03-29

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Jason D. Kohl ,  Pak-Kin Mak ,  Vesselina K. Papazova

IPC: G06F12/0877

CPC classification number: G06F12/0877 ,  G06F12/084 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/502

Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.

公开(公告)号：US20230305966A1

公开(公告)日：2023-09-28

申请号：US17701777

申请日：2022-03-23

Applicant: International Business Machines Corporation

Inventor： Jason D. Kohl ,  Gregory William Alexander ,  Timothy Bronson ,  Akash V. Giri ,  Winston Herring

IPC: G06F12/0895

CPC classification number: G06F12/0895 ,  G06F2212/622

Abstract: A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache’s copy of the cache line until invalidation by the first cache is complete.

公开(公告)号：US20200264797A1

公开(公告)日：2020-08-20

申请号：US16280641

申请日：2019-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jason D. Kohl ,  Tim Bronson ,  Hieu T. Huynh ,  Michael Andrew Blake

IPC: G06F3/06

Abstract: Methods, systems and computer program products for evacuating memory from a drawer in a live multi-node system are provided. Aspects include placing a first drawer into an evacuation mode. The evacuation mode includes a cessation of non-evacuation operations and provides for a transfer of data stored by memory of the first drawer to a destination drawer using dynamic memory reallocation (DMR). Aspects also include transmitting a store request by the first drawer to the destination drawer. The store request represents a request to transfer the data stored by the memory of the first drawer to the destination drawer for storage by the destination drawer. Aspects also include transmitting the data stored by the memory of the first drawer to the destination drawer. The data is transmitted by the first drawer using a local pool of fetch/store controllers.

公开(公告)号：US10339064B2

公开(公告)日：2019-07-02

申请号：US15472610

申请日：2017-03-29

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Jason D. Kohl ,  Pak-Kin Mak ,  Vesselina K. Papazova

IPC: G06F13/18 ,  G06F12/0877

Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.

公开(公告)号：US10325049B2

公开(公告)日：2019-06-18

申请号：US15408449

申请日：2017-01-18

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F17/50

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.