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    Modified central serialization of requests in multiprocessor systems
    1.
    发明授权
    Modified central serialization of requests in multiprocessor systems 有权

    公开(公告)号：US10942775B2

    公开(公告)日：2021-03-09

    申请号：US16289698

    申请日：2019-03-01

    申请人： International Business Machines Corporation

    发明人： Michael A. Blake ,  Arun Iyengar

    IPC分类号： G06F9/50 ,  G06F9/48

    摘要： Embodiments includes a computer-implemented method, a system and computer-program product for modifying central serialization of requests in multiprocessor systems. Some embodiments includes receiving an operation requiring resources from a pool of resources, determining an availability of the pool of resources required by the operation, and selecting a queue of a plurality of queues to queue the operation based at least in part on the availability of the pool of resources. Some embodiments also include setting a resource needs register and needs register for the selected queue, and setting a take-two bit for the selected queue.

    BITLINE DELETION
    7.
    发明申请
    BITLINE DELETION 有权

    公开(公告)号：US20130339809A1

    公开(公告)日：2013-12-19

    申请号：US13788744

    申请日：2013-03-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Hieu T. Huynh ,  Patrick J. Meaney ,  Arthur J. O'Neill

    IPC分类号： G06F11/08

    CPC分类号： G06F11/1064 ,  G06F11/073 ,  G06F11/076 ,  G06F11/08 ,  G11C2029/1204

    摘要： Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses.

    摘要翻译： 实施例涉及用于位线删除的计算机系统，该系统包括高速缓存控制器和高速缓存。 该系统被配置为执行一种方法，包括当读取第一高速缓存线时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误，记录第二错误的第二地址，比较 第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三高速缓存线时检测第三错误，记录第三位线地址 将第二位线地址与第三位线地址进行比较，并且基于激活的位线删​​除模式和匹配的第三和第二位线地址来删除与第三高速缓存线对应的位置。