公开(公告)号：US11099989B2

公开(公告)日：2021-08-24

申请号：US16299287

申请日：2019-03-12

Applicant: International Business Machines Corporation

Inventor： Kevin Lopes ,  Deanna P. D. Berger ,  Chad G. Wilson

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0817

Abstract: Utilizing physical cache address comparison for maintaining coherency. Operations are performed on data in lines of a cache of the computing system and virtual addresses are loaded into a cache controller. The virtual addresses correspond with lines associated with performing the operations. A physical address of a line is determined in response to having performed a first cache directory lookup of the line. The physical address from the first operation is compared with other physical addresses associated with other operations to determine whether the other operations utilize the same physical address as the first operation. In response to matching physical locations, determinations are made as to whether a conflict exists in the data at the physical addresses that match. Thus, the coherency maintenance is free from looking up virtual addresses to determine whether the line of the cache includes incoherent data.

公开(公告)号：US20200301832A1

公开(公告)日：2020-09-24

申请号：US16360468

申请日：2019-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin Lopes ,  Deanna P.D. Berger ,  Jason D Kohl ,  Robert J Sonnelitter, III

IPC: G06F12/084 ,  G06F3/06

Abstract: Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.

公开(公告)号：US10915461B2

公开(公告)日：2021-02-09

申请号：US16292762

申请日：2019-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Robert J. Sonnelitter, III ,  Matthias Klein ,  Craig Walters ,  Kevin Lopes ,  Michael A. Blake ,  Tim Bronson ,  Kenneth Klapproth ,  Vesselina Papazova ,  Hieu T Huynh

IPC: G06F12/126 ,  G06F12/084 ,  G06F12/0811

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

公开(公告)号：US20200293448A1

公开(公告)日：2020-09-17

申请号：US16299287

申请日：2019-03-12

Applicant: International Business Machines Corporation

Inventor： Kevin Lopes ,  Deanna P. D. Berger ,  Chad G. Wilson

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F12/0875

Abstract: Utilizing physical cache address comparison for maintaining coherency. Operations are performed on data in lines of a cache of the computing system and virtual addresses are loaded into a cache controller. The virtual addresses correspond with lines associated with performing the operations. A physical address of a line is determined in response to having performed a first cache directory lookup of the line. The physical address from the first operation is compared with other physical addresses associated with other operations to determine whether the other operations utilize the same physical address as the first operation. In response to matching physical locations, determinations are made as to whether a conflict exists in the data at the physical addresses that match. Thus, the coherency maintenance is free from looking up virtual addresses to determine whether the line of the cache includes incoherent data.

公开(公告)号：US20240119000A1

公开(公告)日：2024-04-11

申请号：US17962829

申请日：2022-10-10

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Matthias Klein ,  Sascha Junghans ,  Kevin Lopes

IPC: G06F12/0802 ,  G06F13/16

CPC classification number: G06F12/0802 ,  G06F13/1668 ,  G06F2212/621

Abstract: A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.

公开(公告)号：US10891232B2

公开(公告)日：2021-01-12

申请号：US16360468

申请日：2019-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin Lopes ,  Deanna P. D. Berger ,  Jason D Kohl ,  Robert J Sonnelitter, III

IPC: G06F12/00 ,  G06F12/084 ,  G06F3/06

Abstract: Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.

公开(公告)号：US20200285592A1

公开(公告)日：2020-09-10

申请号：US16292762

申请日：2019-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Robert J. Sonnelitter, III ,  Matthias Klein ,  Craig Walters ,  Kevin Lopes ,  Michael A. Blake ,  Tim Bronson ,  Kenneth Klapproth ,  Vesselina Papazova ,  Hieu T Huynh

IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/084

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.