公开(公告)号：US10482015B2

公开(公告)日：2019-11-19

申请号：US15598837

申请日：2017-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Ashraf ElSharif ,  Kenneth D. Klapproth ,  Vesselina K. Papazova ,  Guy G. Tracy

IPC: G06F12/0817 ,  G06F12/0891

Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.

公开(公告)号：US20180336135A1

公开(公告)日：2018-11-22

申请号：US15817717

申请日：2017-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Ashraf ElSharif ,  Kenneth D. Klapproth ,  Vesselina K. Papazova ,  Guy G. Tracy

IPC: G06F12/0817 ,  G06F12/0891

Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.

公开(公告)号：US20230315633A1

公开(公告)日：2023-10-05

申请号：US17712510

申请日：2022-04-04

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Richard Joseph Branciforte ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Aaron Tsai ,  Taylor J. Pritchard ,  Markus Kaltenbach ,  Christian Jacobi ,  Michael A. Blake

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

公开(公告)号：US10325049B2

公开(公告)日：2019-06-18

申请号：US15408449

申请日：2017-01-18

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F17/50

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

公开(公告)号：US11977486B2

公开(公告)日：2024-05-07

申请号：US17712510

申请日：2022-04-04

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Richard Joseph Branciforte ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Aaron Tsai ,  Taylor J. Pritchard ,  Markus Kaltenbach ,  Christian Jacobi ,  Michael A. Blake

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

公开(公告)号：US10956637B2

公开(公告)日：2021-03-23

申请号：US16405467

申请日：2019-05-07

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F30/30 ,  G06F30/327 ,  G06F117/02

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

公开(公告)号：US20180203968A1

公开(公告)日：2018-07-19

申请号：US15408449

申请日：2017-01-18

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F2217/70

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.

公开(公告)号：US11880304B2

公开(公告)日：2024-01-23

申请号：US17664722

申请日：2022-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Taylor J Pritchard ,  Aaron Tsai ,  Richard Joseph Branciforte ,  Ashraf ElSharif ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Michael Fee

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/1021

Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

公开(公告)号：US20230385195A1

公开(公告)日：2023-11-30

申请号：US17664722

申请日：2022-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Taylor J. Pritchard ,  Aaron Tsai ,  Richard Joseph Branciforte ,  Ashraf ElSharif ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Michael Fee

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/1021

Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

公开(公告)号：US20190266305A1

公开(公告)日：2019-08-29

申请号：US16405467

申请日：2019-05-07

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Kenneth Douglas Klapproth ,  Jason D. Kohl

IPC: G06F17/50

Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.