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公开(公告)号：US20190384352A1
公开(公告)日：2019-12-19
申请号：US16556206
申请日：2019-08-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael B. Spear , Gary A. Van Huben , Stephen D. Wyatt
摘要： A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.
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公开(公告)号：US10608763B2
公开(公告)日：2020-03-31
申请号：US15988869
申请日：2018-05-24
摘要： Method and apparatus for packeted analysis, comprising: testing a phase rotator at a plurality of phase rotator positions, by propagating a first series of bits of a first pattern through a channel of an integrated circuit; propagating a second series of bits of a second pattern through the channel; measuring, for the given phase rotator position, a value of each bit propagated through the channel; and in response to determining that measured values of the bits propagated through the channel conform to one of the first pattern and the second pattern, indicating that the given phase rotator position satisfies an accuracy threshold; determining a sequence of phase rotator positions of the plurality of phase rotator positions in which the accuracy threshold is satisfied; and in response to determining that the sequence of phase rotator positions does not satisfy an eye width threshold, failing the channel of the integrated circuit.
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公开(公告)号：US10162773B1
公开(公告)日：2018-12-25
申请号：US15813285
申请日：2017-11-15
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael B. Spear , Gary A. Van Huben , Stephen D. Wyatt
IPC分类号： G06F13/16 , G11C7/10 , G11C11/4076 , G06F5/06
摘要： A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.
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公开(公告)号：US10771068B2
公开(公告)日：2020-09-08
申请号：US15899370
申请日：2018-02-20
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael W. Harper , Michael B. Spear , Gary A. Van Huben
摘要： A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.
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5.发明授权Power reduction in a parallel data communications interface using clock resynchronization 有权并行数据通信接口中的功耗降低，使用时钟重新同步公开(公告)号：US09474034B1
公开(公告)日：2016-10-18
申请号：US14954418
申请日：2015-11-30
CPC分类号： G06F1/3253 , G06F1/3206 , G06F1/3287 , H04L7/08 , H04W24/08 , H04W56/001 , Y02D70/00
摘要： A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization.
摘要翻译： 数字数据通信机构包括多条并行线路，其中一条或多条线路的组件被暂时断电以节省功率。 优选地，发射机和接收机都包含相应的生成器，其生成相同的预定义伪随机比特流，它们最初是同步的，并且当线路暂时断电时保持加电。 在重新为线路供电时，发射机发送本地生成的比特流，并且接收机将接收到的比特流与其内部生成的比特流进行比较，以确定重新同步所需的移位量。
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公开(公告)号：US11907074B2
公开(公告)日：2024-02-20
申请号：US17484415
申请日：2021-09-24
发明人： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Michael B. Spear
CPC分类号： G06F11/1423 , G06F5/06 , G06F11/0745 , G06F13/28 , G06F13/385
摘要： Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.
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公开(公告)号：US20230115533A1
公开(公告)日：2023-04-13
申请号：US17484415
申请日：2021-09-24
发明人： Patrick James Meaney , Ashutosh Mishra , Paul Allen Ganfield , Christian Jacobi , Logan Ian Friedman , Jentje Leenstra , Glenn David Gilda , Michael B. Spear
摘要： Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.
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公开(公告)号：US11099601B2
公开(公告)日：2021-08-24
申请号：US16556206
申请日：2019-08-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael B. Spear , Gary A. Van Huben , Stephen D. Wyatt
摘要： A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.
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公开(公告)号：US20190260380A1
公开(公告)日：2019-08-22
申请号：US15899370
申请日：2018-02-20
发明人： Steven R. Carlough , Susan M. Eickhoff , MICHAEL W. HARPER , Michael B. Spear , Gary A. Van Huben
摘要： A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.
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公开(公告)号：US11973630B1
公开(公告)日：2024-04-30
申请号：US18059264
申请日：2022-11-28
CPC分类号： H04L27/364 , H04L27/0014 , H04L2027/0018
摘要： An enhanced quadrature receive serial interface circuit and methods are provided for calibrating the quadrature receive serial interface circuit. A quadrature receive serial interface circuit comprises a first phase rotator and a second phase rotator generating quadrature clocks of identical frequency. Calibration of the quadrature receive serial interface circuit uses a pseudo random bit sequence (PRBS) received by the quadrature receive serial interface circuit. For calibration, one-half of the received PRBS bits are sampled and the phase rotator generating in-phase 0° and 180° clock signals is adjusted to center the data eye for the sampled half of the PRBS bits. Then all data bits (even and odd data bits) of the received PRBS bits are sampled and the phase rotator generating quadrature phase 90° and 270° clock signals is adjusted to center the data eye of all data bits of the PRBS bits to complete calibration.
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