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    ENSURING DATA INTEGRITY IN POWER DOMAIN CROSSING FIFO QUEUES
    2.
    发明公开
    ENSURING DATA INTEGRITY IN POWER DOMAIN CROSSING FIFO QUEUES 审中-公开

    公开(公告)号：US20240303216A1

    公开(公告)日：2024-09-12

    申请号：US18181422

    申请日：2023-03-09

    申请人： QUALCOMM Incorporated

    发明人： Rohit GUPTA ,  Shubham MAHESHWARI ,  Mayukh MALLIK

    IPC分类号： G06F15/78 ,  G06F5/06

    CPC分类号： G06F15/7807 ,  G06F5/06

    摘要： Aspects of the present disclosure provide techniques and apparatus for transferring data, such as between power domains via a first in, first out (FIFO) queue. An example method of transferring data includes selecting, via a source multiplexer, a first memory location included in a FIFO queue and storing first data, where the source multiplexer and the FIFO queue are in a first power domain; outputting the first data to a first level shifter; calculating, in the first power domain, a first value based on the first data; outputting the first value to a second level shifter; selecting, via at least one destination multiplexer included in a second power domain, the first level shifter and the second level shifter; calculating, in the second power domain, a second value based on the first data; and comparing the first value to the second value to generate a result.

    Multichip package with protocol-configurable data paths
    3.
    发明授权
    Multichip package with protocol-configurable data paths 有权

    公开(公告)号：US12086088B2

    公开(公告)日：2024-09-10

    申请号：US18306100

    申请日：2023-04-24

    申请人： Altera Corporation

    发明人： Huy Ngo ,  Keith Duwel ,  David W. Mendel

    IPC分类号： G06F13/40 ,  G06F5/06 ,  G06F13/42

    CPC分类号： G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

    摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

    Object-Oriented Memory
    4.
    发明公开
    Object-Oriented Memory 审中-公开

    公开(公告)号：US20240220322A1

    公开(公告)日：2024-07-04

    申请号：US18609659

    申请日：2024-03-19

    申请人： Marvell Asia Pte, Ltd.

    发明人： Nathan Chrisman

    IPC分类号： G06F9/50 ,  G06F5/06 ,  G06F9/38 ,  G06F9/448 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0893 ,  G06F13/16

    CPC分类号： G06F9/5016 ,  G06F5/065 ,  G06F9/3818 ,  G06F9/3877 ,  G06F9/4488 ,  G06F9/546 ,  G06F9/548 ,  G06F11/1004 ,  G06F12/0253 ,  G06F12/0893 ,  G06F13/1673 ,  G06F2213/0026

    摘要： A system and corresponding method employ an object-oriented memory device. The object-oriented memory device includes at least one physical memory and a hardware controller. The hardware controller is coupled intra the object-oriented memory device to the at least one physical memory. The hardware controller (i) decodes an object-oriented message received from a hardware client of the object-oriented memory device and (ii) performs an action for the hardware client based on the object-oriented message received and decoded. The object-oriented message is associated with an object instantiated or to-be-instantiated in the at least one physical memory. The action is associated with the object. The object-oriented memory device alleviates the hardware client(s) from having to manage structure of respective data stored in the at least one physical memory, obviating duplication of code among the hardware clients for managing same and efforts for design and verification thereof.

    Modular sequencer for radar applications
    6.
    发明授权
    Modular sequencer for radar applications 有权

    公开(公告)号：US12000952B2

    公开(公告)日：2024-06-04

    申请号：US16949251

    申请日：2020-10-21

    申请人： Infineon Technologies AG

    发明人： Rainer Findenig ,  Bernhard Greslehner-Nimmervoll

    IPC分类号： G01S7/35 ,  G06F5/06 ,  G06F13/16

    CPC分类号： G01S7/35 ,  G06F5/06 ,  G06F13/1673 ,  G06F13/1689

    摘要： A radar device may include a memory to store a program associated with operating the radar device. The radar device may include a decoder to read the program from the memory, and generate a control value and a timestamp based at least in part on the program. The control value may be a value to be provided as an input to a component of the radar device at a time indicated by the timestamp. The radar device may include a first-in first-out (FIFO) buffer to store at least the control value and provide the control value as the input to the component of the radar device at the time indicated by the timestamp.

    Multi-rendering in graphics processing units using render progression checks
    9.
    发明授权
    Multi-rendering in graphics processing units using render progression checks 有权

    公开(公告)号：US11887240B2

    公开(公告)日：2024-01-30

    申请号：US17578774

    申请日：2022-01-19

    申请人： Imagination Technologies Limited

    发明人： John Howson ,  Steven Fishwick

    IPC分类号： G06T5/00 ,  G06F5/06 ,  G06F9/48 ,  G06T1/20 ,  G06T15/00

    CPC分类号： G06T15/005 ,  G06F5/06 ,  G06F9/4881 ,  G06T1/20

    摘要： A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.

    MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS
    10.
    发明公开
    MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS 审中-公开

    公开(公告)号：US20230289309A1

    公开(公告)日：2023-09-14

    申请号：US18306100

    申请日：2023-04-24

    申请人： Altera Corporation

    发明人： Huy Ngo ,  Keith Duwel ,  David W. Mendel

    IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F5/06

    CPC分类号： G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

    摘要： Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.