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    RENDERING VIEWS OF A SCENE IN A GRAPHICS PROCESSING UNIT
    2.
    发明公开
    RENDERING VIEWS OF A SCENE IN A GRAPHICS PROCESSING UNIT 审中-公开

    公开(公告)号：US20240233270A1

    公开(公告)日：2024-07-11

    申请号：US18615489

    申请日：2024-03-25

    申请人： Imagination Technologies Limited

    发明人： Steven Fishwick

    IPC分类号： G06T17/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/00 ,  G06T15/04 ,  G06T15/80

    CPC分类号： G06T17/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T15/04 ,  G06T15/80 ,  G06T2200/04 ,  G06T2200/28

    摘要： Graphics processing systems may render multiple views of a scene (e.g. a sequence of frames) in a tile-based manner. Groups of views may be rendered together such that tiles from a group of views are rendered in an interspersed order such that at least one tile from each of the views in the group is rendered before any of the views of the scene in the group are fully rendered. In this way similar tiles from different views within a group may be rendered sequentially. If a particular rendered tile is similar to the next tile to be rendered then data stored in a cache for rendering the particular tile is likely to be useful for rendering the next tile. Therefore, when rendering the next tile less data needs to be fetched from the system memory which can significantly improve the efficiency of the graphics processing system.

    Controlling Rendering Operations by Shader Buffer Identification
    3.
    发明申请
    Controlling Rendering Operations by Shader Buffer Identification 有权

    公开(公告)号：US20220157007A1

    公开(公告)日：2022-05-19

    申请号：US17587008

    申请日：2022-01-28

    申请人： Imagination Technologies Limited

    发明人： John W. Howson ,  Aroun Demeure ,  Steven Fishwick

    IPC分类号： G06T15/00 ,  G06F8/41 ,  G06T1/20 ,  G06T15/80 ,  G09G5/36

    摘要： Methods of rendering a scene in a graphics system identify a draw call within a current render and analyse the last shader in the series of shaders used by the draw call to identify any buffers that are sampled by the last shader and that are to be written by a previous render that has not yet been sent for execution on the GPU. If any such buffers are identified, further analysis is performed to determine whether the last shader samples from the identified buffers using screen space coordinates that correspond to a current fragment location and if this determination is positive, the draw call is added to data relating to the previous render and the last shader is recompiled to replace an instruction that reads data from an identified buffer with an instruction that reads data from an on-chip register.

    Multi-Rendering in Graphics Processing Units Using Render Progression Checks
    5.
    发明申请
    Multi-Rendering in Graphics Processing Units Using Render Progression Checks 审中-公开

    公开(公告)号：US20200380755A1

    公开(公告)日：2020-12-03

    申请号：US16888763

    申请日：2020-05-31

    申请人： Imagination Technologies Limited

    发明人： John Howson ,  Steven Fishwick

    IPC分类号： G06T15/00 ,  G06F9/48 ,  G06T1/20 ,  G06F5/06

    摘要： A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.

    Graphics processing units and methods using cost indications for sets of tiles of a rendering space
    8.
    发明授权
    Graphics processing units and methods using cost indications for sets of tiles of a rendering space 有权

    公开(公告)号：US10249016B2

    公开(公告)日：2019-04-02

    申请号：US15868694

    申请日：2018-01-11

    申请人： Imagination Technologies Limited

    发明人： Richard Broadhurst ,  John W. Howson ,  Steven Fishwick

    IPC分类号： G06T1/20 ,  G06T15/00 ,  G09G5/36

    摘要： A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. The graphics processing unit also comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles. The graphics processing unit also comprises scheduling logic configured to schedule, in dependence upon the cost indications, the sets of one or more tiles for processing on the one or more processing cores.

    Multi-rendering in graphics processing units using render progression checks
    10.
    发明授权
    Multi-rendering in graphics processing units using render progression checks 有权

    公开(公告)号：US11887240B2

    公开(公告)日：2024-01-30

    申请号：US17578774

    申请日：2022-01-19

    申请人： Imagination Technologies Limited

    发明人： John Howson ,  Steven Fishwick

    IPC分类号： G06T5/00 ,  G06F5/06 ,  G06F9/48 ,  G06T1/20 ,  G06T15/00

    CPC分类号： G06T15/005 ,  G06F5/06 ,  G06F9/4881 ,  G06T1/20

    摘要： A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.