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公开(公告)号：US20240221290A1
公开(公告)日：2024-07-04
申请号：US18601621
申请日：2024-03-11
发明人： John Howson
CPC分类号： G06T15/405 , G06T15/005 , G06T15/30 , G06T15/40 , G06T19/20
摘要： A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values from either the PDB or the SDB. When a fragment passes a depth test, its depth value is stored in the PDB if it is a resolved fragment (e.g. if it is opaque or translucent), and its depth value is stored in the SDB if it is an unresolved fragment (e.g. if it is a punch through fragment). This provides more opportunities for subsequent opaque objects to overwrite punch through fragments which passed a depth test, thereby reducing unnecessary processing and time which may be spent on fragments which ultimately will not contribute to the final rendered image.
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公开(公告)号：US20240169642A1
公开(公告)日：2024-05-23
申请号：US18426221
申请日：2024-01-29
发明人： John Howson , Steven Fishwick
CPC分类号： G06T15/005 , G06F5/06 , G06F9/4881 , G06T1/20
摘要： A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.
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公开(公告)号：US11734788B2
公开(公告)日：2023-08-22
申请号：US17515278
申请日：2021-10-29
发明人： John Howson , Jonathan Redshaw , Yoong Chert Foo
CPC分类号： G06T1/20 , G06F9/30036 , G06F9/3822 , G06F9/3836 , G06F9/3887 , G06F15/8007 , G06F9/4881 , G06F2209/507
摘要： A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
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公开(公告)号：US11263798B2
公开(公告)日：2022-03-01
申请号：US16888763
申请日：2020-05-31
发明人： John Howson , Steven Fishwick
摘要： A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.
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公开(公告)号：US11176733B2
公开(公告)日：2021-11-16
申请号：US16735201
申请日：2020-01-06
发明人： John Howson
摘要： A graphics processing system performs hidden surface removal and texturing/shading on fragments of primitives. The system includes a primary depth buffer (PDB) for storing depth values of resolved fragments, and a secondary depth buffer (SDB) for storing depth values of unresolved fragments. Incoming fragments are depth tested against depth values from either the PDB or the SDB. When a fragment passes a depth test, its depth value is stored in the PDB if it is a resolved fragment (e.g. if it is opaque or translucent), and its depth value is stored in the SDB if it is an unresolved fragment (e.g. if it is a punch through fragment). This provides more opportunities for subsequent opaque objects to overwrite punch through fragments which passed a depth test, thereby reducing unnecessary processing and time which may be spent on fragments which ultimately will not contribute to the final rendered image.
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公开(公告)号：US11080926B2
公开(公告)日：2021-08-03
申请号：US16683085
申请日：2019-11-13
发明人： Richard Broadhurst , John Howson , Robert Theed
摘要： A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.
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公开(公告)号：US20190244325A1
公开(公告)日：2019-08-08
申请号：US16386840
申请日：2019-04-17
发明人： John Howson , Jonathan Redshaw , Yoong Chert Foo
CPC分类号： G06T1/20 , G06F9/30036 , G06F9/3822 , G06F9/3836 , G06F9/3887 , G06F9/4881 , G06F15/8007 , G06F2209/507
摘要： A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
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公开(公告)号：US20170148130A1
公开(公告)日：2017-05-25
申请号：US15424168
申请日：2017-02-03
发明人： Steven John Fishwick , John Howson
IPC分类号： G06T1/20 , G06F12/126 , G06F12/0875 , G06F12/0891 , G06T1/60 , G06T15/00
CPC分类号： G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06F12/0891 , G06F12/12 , G06F12/126 , G06F2212/1021 , G06F2212/302 , G06F2212/45 , G06F2212/70 , G06T1/60 , G06T15/00 , G06T15/005
摘要： A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.
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9.发明申请Task Execution in a SIMD Processing Unit with Parallel Groups of Processing Lanes 审中-公开具有并行加工车道组的SIMD处理单元中的任务执行公开(公告)号：US20170076420A1
公开(公告)日：2017-03-16
申请号：US15341884
申请日：2016-11-02
发明人： John Howson , Jonathan Redshaw , Yoong Chert Foo
CPC分类号： G06T1/20 , G06F9/30036 , G06F9/3822 , G06F9/3836 , G06F9/3887 , G06F9/4881 , G06F15/8007 , G06F2209/507
摘要： A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
摘要翻译： SIMD处理单元处理多个任务，每个任务包括多达预定的最大数目的工作项。 任务的工作项目被安排用于对各个数据项执行公共的指令序列。 数据项被排列成块，其中一些块包括至少一个无效数据项。 与无效数据项相关的工作项是无效的工作项。 SIMD处理单元包括一组处理通道，其被配置为在多个处理循环中执行特定任务的工作项目的指令。 控制模块基于工作项的有效性将工作项目组合到任务中，使得特定任务的无效工作项在时间上跨越处理通道进行对齐。 以这种方式，可以减少由于无效的工作项造成的浪费的处理槽的数量。
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公开(公告)号：US11954759B2
公开(公告)日：2024-04-09
申请号：US18076803
申请日：2022-12-07
发明人： Steven Fishwick , John Howson
IPC分类号： G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06F12/0891 , G06F12/126 , G06T1/60 , G06T15/00 , G06F12/12
CPC分类号： G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06F12/0891 , G06F12/126 , G06T1/60 , G06T15/00 , G06T15/005 , G06F12/12 , G06F2212/1021 , G06F2212/302 , G06F2212/45 , G06F2212/70
摘要： A tile-based graphics system has a rendering space sub-divided into a plurality of tiles which are to be processed. Graphics data items, such as parameters or texels, are fetched into a cache for use in processing one of the tiles. Indicators are determined for the graphics data items, whereby the indicator for a graphics data item indicates the number of tiles with which that graphics data item is associated. The graphics data items are evicted from the cache in accordance with the indicators of the graphics data items. For example, the indicator for a graphics data item may be a count of the number of tiles with which that graphics data item is associated, whereby the graphics data item(s) with the lowest count(s) is (are) evicted from the cache.
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