公开(公告)号：US11928578B2

公开(公告)日：2024-03-12

申请号：US17108927

申请日：2020-12-01

Applicant: POSTECH Research and Business Development Foundation

Inventor： Sungju Ryu ,  Jae-Joon Kim ,  Youngtaek Oh

IPC: G06F5/06 ,  G06F7/76 ,  G06F17/15 ,  G06F17/16 ,  G06N3/047 ,  G06N3/063

CPC classification number: G06N3/063 ,  G06F5/06 ,  G06F7/76 ,  G06F17/15 ,  G06F17/16 ,  G06N3/047 ,  G06F5/065

Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.

公开(公告)号：US11335399B2

公开(公告)日：2022-05-17

申请号：US17011929

申请日：2020-09-03

Applicant: Postech Research and Business Development Foundation

Inventor： Jinseok Kim ,  Yulhwa Kim ,  Jae-Joon Kim ,  Hyungjun Kim

IPC: G11C11/41 ,  G06N3/08 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

公开(公告)号：US11483003B2

公开(公告)日：2022-10-25

申请号：US17298917

申请日：2019-12-09

Applicant: POSTECH Research and Business Development Foundation

Inventor： Eun Hwan Kim ,  Jae-Joon Kim

IPC: H03K19/0944

Abstract: A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.