公开(公告)号：US11335399B2

公开(公告)日：2022-05-17

申请号：US17011929

申请日：2020-09-03

Applicant: Postech Research and Business Development Foundation

Inventor： Jinseok Kim ,  Yulhwa Kim ,  Jae-Joon Kim ,  Hyungjun Kim

IPC: G11C11/41 ,  G06N3/08 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.