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公开(公告)号：US11669479B2
公开(公告)日：2023-06-06
申请号：US17711860
申请日：2022-04-01
Applicant: Altera Corporation
Inventor： Huy Ngo , Keith Duwel , David W. Mendel
CPC classification number: G06F13/4022 , G06F5/065 , G06F13/4018 , G06F13/4291 , G06F2205/067
Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.
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公开(公告)号：US20210109882A1
公开(公告)日：2021-04-15
申请号：US17131474
申请日：2020-12-22
Applicant: Altera Corporation
Inventor： Huy Ngo , Keith Duwel , David W. Mendel
Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.
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公开(公告)号：US10296479B1
公开(公告)日：2019-05-21
申请号：US14975370
申请日：2015-12-18
Applicant: ALTERA CORPORATION
Inventor： Gregg William Baeckler , David W. Mendel
Abstract: The present disclosure provides an innovative circuit structure for control insertion into a multiple-word wide data stream. The control-insertion circuit structure is advantageously scalable as the data width increases. An exemplary implementation of the control-insertion circuit structure includes a multiple-layer shifting circuit. The multiple-layer shifting circuit has some similarities with a barrel shifter. However, unlike a barrel shifter, the multiple-layer shifting circuit moves data words in both directions and moves portions of the data to create spaces or holes in the data (rather than moving the entire width as a barrel shifter does). The output of the multiple-layer shifting circuit is a “swiss-cheese-like” structure of data, where the spaces or holes in the data are available for control insertion. Other features, aspects and embodiments are also disclosed.
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公开(公告)号：US10291442B2
公开(公告)日：2019-05-14
申请号：US15684310
申请日：2017-08-23
Applicant: ALTERA CORPORATION
Inventor： David W. Mendel , Han Hua Leong
IPC: H04L25/14 , H04L12/24 , H04L12/26 , H04L12/875 , G06F5/06
Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.
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公开(公告)号：US09118566B1
公开(公告)日：2015-08-25
申请号：US13764601
申请日：2013-02-11
Applicant: ALTERA CORPORATION
Inventor： David W. Mendel , Herman Schmit
CPC classification number: H04L43/106 , H04L43/0858
Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using a predetermined function of the word arrival times. Another embodiment relates to a receiver circuit that determines an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Other embodiments and features are also disclosed.
Abstract translation: 一个实施例涉及一种确定数据分组的到达时间的方法，该数据分组具有跨多通道链路的多个通道的条带。 确定数据包的字的字到达时间，每个字的到达时间对应于多车道链路的单独车道上的数据包的字的到达时间。 使用字到达时间的预定函数来确定数据分组的到达时间。 另一个实施例涉及一种接收机电路，其确定数据分组的到达时间，该数据分组具有穿过多通道链路的多个通道的条带。 还公开了其它实施例和特征。
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Patent Agency Ranking
公开(公告)号：US09048889B1
公开(公告)日：2015-06-02
申请号：US14075861
申请日：2013-11-08
Applicant: Altera Corporation
Inventor： Divya Vijayaraghavan , David W. Mendel , Gregg William Baeckler
CPC classification number: G06F13/4291
Abstract: The present disclosure provides physical coding sublayer architectures that enable high-speed serial interfaces capable of operating at data rates ranging from 400 gigabits per second (Gbps) to 1 terabit per second (Tbps). A first embodiment relates to an architecture that provides an aggregated physical coding sublayer (PCS) that provides multiple virtual lanes. A second embodiment relates to an architecture that has a channel-based PCS and provides an aggregation layer above the PCS channels. A third embodiment relates to an architecture that, like the second embodiment, has a channel-based PCS and provides an aggregation layer above the PCS channels. However, each channel-based PCS in the third embodiment provides multiple virtual lanes. Other embodiments, aspects and features are also disclosed.
Abstract translation: 本公开提供了物理编码子层架构，其使得能够以从每秒400吉比特（Gbps）到每秒1兆比特（Tbps）的数据速率进行操作的高速串行接口。 第一实施例涉及提供提供多个虚拟通道的聚合物理编码子层（PCS）的架构。 第二实施例涉及具有基于信道的PCS并在PCS信道上提供聚合层的体系结构。 第三实施例涉及与第二实施例类似的具有基于通道的PCS并且在PCS信道上方提供聚合层的架构。 然而，第三实施例中的基于通道的PCS提供多个虚拟通道。 还公开了其它实施例，方面和特征。
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公开(公告)号：US20140269983A1
公开(公告)日：2014-09-18
申请号：US13799231
申请日：2013-03-13
Applicant: Altera Corporation
Inventor： Gregg William Baeckler , David W. Mendel
IPC: H04L1/00
CPC classification number: H04L1/009 , H04L1/203 , H04L25/0284 , H04L25/4915
Abstract: An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link.
Abstract translation: 一种装置包括适于将编码信息发送到通信链路的发射机。 发射机包括直流平衡偏斜发生器。 直流平衡偏斜发生器适于在将信息提供给通信链路之前扭曲信息的直流平衡。
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8.发明申请公开(公告)号：US20140198810A1
公开(公告)日：2014-07-17
申请号：US13742775
申请日：2013-01-16
Applicant: Altera Corporation
Inventor： Jakob Raymond Jones , David W. Mendel
IPC: H04L7/00
CPC classification number: H03L7/0814 , G06F1/10
Abstract: A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave clock signal received at the master transceiver channel to obtain a total adjustment value. The phase of the intermediate slave clock signal may further be adjusted at the slave transceiver channel based on the total adjustment made at the master transceiver channel.
Abstract translation: 在集成电路上的多个收发器通道中对准时钟信号的方法可以包括基于从主收发器通道接收的主时钟信号来调整从收发器通道处的从时钟信号。 从收发器通道中的时钟发生电路和/或延迟电路可用于调整从时钟信号以产生中间从时钟信号。 可以基于在主收发器通道处接收的中间从时钟信号来调整主时钟信号以获得总调整值。 基于在主收发器信道进行的总调整，中间从时钟信号的相位可进一步在从收发器信道被调整。
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公开(公告)号：US20130207688A1
公开(公告)日：2013-08-15
申请号：US13843385
申请日：2013-03-15
Applicant: Altera Corporation
Inventor： Sinan Kaptanoglu , David W. Mendel
IPC: H03K19/177
CPC classification number: H03K19/17748 , H03K19/017581 , H03K19/177 , H03K19/17728 , H03K19/1774 , H03K19/17796
Abstract: A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.
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公开(公告)号：US10394737B1
公开(公告)日：2019-08-27
申请号：US14975270
申请日：2015-12-18
Applicant: Altera Corporation
Inventor： Huy Ngo , Keith Duwel , David W. Mendel
Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.
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