公开(公告)号：US09270500B1

公开(公告)日：2016-02-23

申请号：US14106485

申请日：2013-12-13

Applicant: ALTERA CORPORATION

Inventor： Divya Vijayaraghavan ,  Gopi Krishnamurthy ,  Ning Xue ,  Chong H. Lee

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04B3/04 ,  H04B3/32 ,  H04L25/03343

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及被配置为执行双向通道的动态发送均衡的集成电路。 该集成电路包括物理编码和媒体访问控制电路之间的接口，以及在物理编码电路外部的配置成使用所述接口执行动态发送均衡的均衡控制电路。 另一个实施例涉及一种包括物理编码电路和媒体访问控制电路的收发器电路。 收发器电路还包括物理编码电路和媒体访问控制电路之间的接口以及在物理编码电路之外的均衡控制器，并且被配置为使用所述接口执行动态发送均衡。 接口被配置为以时间复用的信号格式提供从媒体访问控制电路到物理编码电路的传输系数数据。 还公开了其它实施例，方面和特征。

公开(公告)号：US10404627B2

公开(公告)日：2019-09-03

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

公开(公告)号：US20180034748A1

公开(公告)日：2018-02-01

申请号：US15676402

申请日：2017-08-14

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  Vinson Chan ,  Divya Vijayaraghavan ,  Curt Wortman

IPC: H04L12/861 ,  H04L12/863

CPC classification number: H04L49/90 ,  H04L47/6245

Abstract: Systems and methods are disclosed for buffering data using a multi-function, multi-protocol first-in-first-out (FIFO) circuit. For example, a data buffering apparatus is provided that includes a mode selection input and a FIFO circuit that is operative to buffer a data signal between a FIFO circuit input and a FIFO circuit output, wherein the FIFO circuit is configured in an operating mode responsive to the mode selection signal.

公开(公告)号：US09048889B1

公开(公告)日：2015-06-02

申请号：US14075861

申请日：2013-11-08

Applicant: Altera Corporation

Inventor： Divya Vijayaraghavan ,  David W. Mendel ,  Gregg William Baeckler

IPC: H04L27/00 ,  H04B1/04 ,  H04B1/16

CPC classification number: G06F13/4291

Abstract: The present disclosure provides physical coding sublayer architectures that enable high-speed serial interfaces capable of operating at data rates ranging from 400 gigabits per second (Gbps) to 1 terabit per second (Tbps). A first embodiment relates to an architecture that provides an aggregated physical coding sublayer (PCS) that provides multiple virtual lanes. A second embodiment relates to an architecture that has a channel-based PCS and provides an aggregation layer above the PCS channels. A third embodiment relates to an architecture that, like the second embodiment, has a channel-based PCS and provides an aggregation layer above the PCS channels. However, each channel-based PCS in the third embodiment provides multiple virtual lanes. Other embodiments, aspects and features are also disclosed.

Abstract translation: 本公开提供了物理编码子层架构，其使得能够以从每秒400吉比特（Gbps）到每秒1兆比特（Tbps）的数据速率进行操作的高速串行接口。 第一实施例涉及提供提供多个虚拟通道的聚合物理编码子层（PCS）的架构。 第二实施例涉及具有基于信道的PCS并在PCS信道上提供聚合层的体系结构。 第三实施例涉及与第二实施例类似的具有基于通道的PCS并且在PCS信道上方提供聚合层的架构。 然而，第三实施例中的基于通道的PCS提供多个虚拟通道。 还公开了其它实施例，方面和特征。

公开(公告)号：US10216219B1

公开(公告)日：2019-02-26

申请号：US15356052

申请日：2016-11-18

Applicant: Altera Corporation

Inventor： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee ,  Vinson Chan

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/08

Abstract: A configurable multi-protocol transceiver implemented in an integrated circuit (“IC”) includes configurable deskew circuitry. The transceiver has various configurable deskew settings to facilitate effectively adapting transmit and/or receive communications corresponding to a selected one of a plurality of high-speed communication protocols and/or adapt to different implementations in which a deskew block addresses either just static skew or both static and dynamic skew. Configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. Configurable circuitry is adapted to control a deskew character transmit insertion frequency. A programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. Configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations.

公开(公告)号：US10374636B1

公开(公告)日：2019-08-06

申请号：US15090170

申请日：2016-04-04

Applicant: ALTERA CORPORATION

Inventor： Haiyun Yang ,  Martin Langhammer ,  Peng Li ,  Divya Vijayaraghavan

IPC: H04L1/00 ,  H03M13/29 ,  H03M13/13

Abstract: One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC encoded at a bus width which is specified within particular constraints. One constraint is that the FEC encoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC encoder bus width. Another constraint may be that the FEC encoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

公开(公告)号：US09331714B1

公开(公告)日：2016-05-03

申请号：US13871227

申请日：2013-04-26

Applicant: ALTERA CORPORATION

Inventor： Haiyun Yang ,  Martin Langhammer ,  Peng Li ,  Divya Vijayaraghavan

IPC: G06F11/00 ,  H03M13/05

CPC classification number: H03M13/05 ,  H03M13/1515 ,  H04L1/20 ,  H04L12/40 ,  H04L12/40013 ,  H04L25/14

Abstract: One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC decoded at a bus width which is specified within particular constraints. One constraint is that the FEC decoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC decoder bus width. Another constraint may be that the FEC decoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及从多通道数据链路接收数据的方法。 数据用具有块长度的FEC码进行编码。 该数据在特定约束条件下指定的总线宽度进行FEC解码。 一个约束是FEC解码器总线宽度（以位为单位）是数据中每个符号数位数的精确倍数。 另一个约束可能是FEC码块长度是FEC解码器总线宽度的精确倍数。 另一个约束可能是FEC解码器总线宽度是多通道接口的多个串行通道的精确倍数。 还公开了其它实施例和特征。

公开(公告)号：US08984380B2

公开(公告)日：2015-03-17

申请号：US13733798

申请日：2013-01-03

Applicant: ALTERA Corporation

Inventor： Divya Vijayaraghavan ,  Chong H. Lee ,  Keith Duwel ,  Vinson Chan

IPC: H03M13/00 ,  H03M13/35 ,  H03M13/37 ,  H04L12/931 ,  H03M13/07

CPC classification number: H03M13/353 ,  H03M13/07 ,  H03M13/3738 ,  H03M13/63 ,  H03M13/6511 ,  H03M13/6516 ,  H03M13/6519 ,  H04L49/604

Abstract: A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Abstract translation: 一种用于操作可配置为在单个设备上支持一个或多个通信标准的通信电路的方法和系统。 通信电路包括：发送装置，其包括以第一数据速率操作的PCS模块和以第二数据速率操作的第二PCS模块。 电路还包括多个前向纠错（FEC）编码和解码模块，每个以指定的数据速率运行。 第一组FEC编码和解码模块被配置为支持第一PCS模块，并且第二组FEC编码和解码模块被配置为支持第二PCS模块。

公开(公告)号：US20140189459A1

公开(公告)日：2014-07-03

申请号：US13733798

申请日：2013-01-03

Applicant: ALTERA Corporation

Inventor： Divya Vijayaraghavan ,  Chong H. Lee ,  Keith Duwel ,  Vinson Chan

IPC: H03M13/29

CPC classification number: H03M13/353 ,  H03M13/07 ,  H03M13/3738 ,  H03M13/63 ,  H03M13/6511 ,  H03M13/6516 ,  H03M13/6519 ,  H04L49/604

Abstract: A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.

Abstract translation: 一种用于操作可配置为在单个设备上支持一个或多个通信标准的通信电路的方法和系统。 通信电路包括：发送装置，其包括以第一数据速率操作的PCS模块和以第二数据速率操作的第二PCS模块。 电路还包括多个前向纠错（FEC）编码和解码模块，每个以指定的数据速率运行。 第一组FEC编码和解码模块被配置为支持第一PCS模块，并且第二组FEC编码和解码模块被配置为支持第二PCS模块。