公开(公告)号：US12088360B2

公开(公告)日：2024-09-10

申请号：US16897135

申请日：2020-06-09

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Diego Correas-Serrano ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing ,  Cooper S. Levy ,  Chintan S. Thakkar ,  Stefano Pellerano

IPC: H04B3/32 ,  H04L25/03

CPC classification number: H04B3/32 ,  H04L25/03885

Abstract: Embodiments may relate to a baseband module with communication pathways for a first data signal and a second data signal. The baseband module may also include a finite impulse response (FIR) filter in a communication path between the first signal input and the second signal output. Other embodiments may be described or claimed.

公开(公告)号：US20240235905A9

公开(公告)日：2024-07-11

申请号：US18368262

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Seungsik EOM ,  Youngjin CHUNG ,  Sangyun HWANG

IPC: H04L25/06 ,  G06F8/65 ,  H04L25/03

CPC classification number: H04L25/061 ,  G06F8/65 ,  H04L25/03885

Abstract: An electronic device includes an analog front end (AFE) circuit including plural modules, and a processor that provides a user interface for a firmware update, determines a target module, of which offset calibration is to be performed, among the plural modules, based on a user input to the user interface, determines a position within in the AFE circuit to which a common mode voltage is to be applied to perform the offset calibration of the target module, and determines an offset calibration sequence including the target module and the position.

公开(公告)号：US20240137252A1

公开(公告)日：2024-04-25

申请号：US18368262

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Seungsik EOM ,  Youngjin CHUNG ,  Sangyun HWANG

IPC: H04L25/06 ,  G06F8/65 ,  H04L25/03

CPC classification number: H04L25/061 ,  G06F8/65 ,  H04L25/03885

Abstract: An electronic device includes an analog front end (AFE) circuit including plural modules, and a processor that provides a user interface for a firmware update, determines a target module, of which offset calibration is to be performed, among the plural modules, based on a user input to the user interface, determines a position within in the AFE circuit to which a common mode voltage is to be applied to perform the offset calibration of the target module, and determines an offset calibration sequence including the target module and the position.

公开(公告)号：US11843484B2

公开(公告)日：2023-12-12

申请号：US18046716

申请日：2022-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suzanne Mary Vining ,  Amit S. Rane ,  Charles Michael Campbell

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03828

Abstract: A system for selecting an equalizer setting of an equalizer to equalize signals received via a communications link. Starting with a first (e.g., minimum) equalizer setting and a threshold voltage near the mid-eye voltage of the equalized output signal, the system estimates the amplitude of the inner eye of the equalized output signal by comparing the equalized output signal to a series of threshold voltages. If the amplitude of the equalized output signal is less than ideal, the system dynamically increases the equalizer setting. The system quickly converges on the equalizer setting for the communication link because, rather than comparing the output signal at every voltage offset using every equalizer setting, the system only evaluates the equalizer settings necessary to select the equalizer setting for the communications link and uses only the voltage offsets necessary to evaluate each equalizer setting.

公开(公告)号：US11665028B2

公开(公告)日：2023-05-30

申请号：US17482659

申请日：2021-09-23

Applicant: Rambus Inc.

Inventor： Ramin Farjad-Rad

IPC: H04B3/14 ,  H04L25/03 ,  H04L1/00 ,  H04B10/40 ,  G06F1/10 ,  G06F3/041 ,  H04L25/08

CPC classification number: H04L25/03159 ,  H04L25/03019 ,  H04L25/03343 ,  H04L25/03885 ,  G06F1/10 ,  G06F3/041 ,  H04B3/145 ,  H04B10/40 ,  H04L1/0071 ,  H04L25/085 ,  H04L2025/03681

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

公开(公告)号：US20230164007A1

公开(公告)日：2023-05-25

申请号：US17698918

申请日：2022-03-18

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Daeho YUN ,  Deog-Kyoon JEONG

IPC: H04L25/03 ,  H04L27/01

CPC classification number: H04L25/03885 ,  H04L25/03057 ,  H04L27/01

Abstract: A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

公开(公告)号：US20190212496A1

公开(公告)日：2019-07-11

申请号：US16352636

申请日：2019-03-13

Applicant: INPHI CORPORATION

Inventor： Samira KARIMELAHI ,  Masaki KATO

IPC: G02B6/293 ,  H04L25/03 ,  H04B10/25 ,  G02B6/28

CPC classification number: G02B6/29391 ,  G02B6/2856 ,  G02B6/29344 ,  G02B6/29352 ,  H04B10/25 ,  H04L25/03885

Abstract: The present disclosure provides an optical equalizer for photonics system in an electric-optical communication network. The optical equalizer includes an input port and an output port. Additionally, the optical equalizer includes a filter having a number of stages coupled to each other in a multi-stage series with an output terminal of any stage being coupled to an input terminal of an adjacent next stage while the input terminal of a first stage of the multi-stage series being coupled from the input port. Each stage includes a tap terminal configured to pass an optical power factored by a coefficient of multiplication from the corresponding input terminal of the stage to a tap-output path characterized by a corresponding phase delay. Furthermore, the optical equalizer includes a combiner configured to sum up the optical powers respectively from the number of tap-output paths of the multi-stage series to the output port.

公开(公告)号：US20190028211A1

公开(公告)日：2019-01-24

申请号：US16142160

申请日：2018-09-26

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida ,  Aviv Salamon ,  Gaby Gur Cohen ,  Israel Greiss

IPC: H04B15/00 ,  H04L25/03 ,  H04B1/38 ,  H04B1/10

CPC classification number: H04B15/00 ,  H04B1/1027 ,  H04B1/38 ,  H04L25/0276 ,  H04L25/03885

Abstract: Methods and systems for rapidly recovering from a serious interference. One method includes the following steps: transmitting, by a transmitter to a transceiver over a communication channel, ongoing data at a fixed data rate above 100 Mbps; receiving, by a receiver from the transceiver, an indication indicating that the transceiver is experiencing a serious interference; responsive to the indication, reducing data rate at which the transmitter transmits; storing excess data that cannot be sent during the period of the reduced data rate; and increasing the data rate, at which the transmitter transmits, to a level that enables it to transmit, within less than 1 millisecond from the moment of reducing the data rate, both the stored excess data and the ongoing data at the fixed data rate.

公开(公告)号：US20180367350A1

公开(公告)日：2018-12-20

申请号：US16010445

申请日：2018-06-16

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fred F. Chen ,  Andrew Ho ,  Ramin Farjad-Rad ,  John W. Poulton ,  Kevin S. Donnelly ,  Brian S. Leibowitz

IPC: H04L27/01 ,  H04L25/03 ,  H04L1/00 ,  H04L7/033 ,  H04L25/497 ,  H04W52/20 ,  H04L7/00 ,  H04L25/02 ,  H04W52/22

CPC classification number: H04L27/01 ,  H04L1/0026 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/497 ,  H04L2025/03503 ,  H04W52/20 ,  H04W52/225 ,  Y02D70/00

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

公开(公告)号：US20180270085A1

公开(公告)日：2018-09-20

申请号：US15895823

申请日：2018-02-13

Applicant: Panasonic Corporation

Inventor： TAKENORI SAKAMOTO ,  YOHEI MORISHITA

IPC: H04L25/02 ,  H04L25/03

CPC classification number: H04L25/022 ,  H03M5/145 ,  H04L25/0204 ,  H04L25/03834 ,  H04L25/03885

Abstract: A radio receiving apparatus includes an RF front-end unit that performs gain control and downconversion on a received signal, an analog equalizer that performs an analog equalization process on an output signal from the RF front-end unit in accordance with a coefficient of analog equalization, an analog/digital converter that samples and quantizes an output signal from the analog equalizer, a digital equalizer that performs a digital equalization process on an output signal from the analog/digital converter in accordance with a coefficient of digital equalization, and a coefficient-of-equalization calculator that calculates the coefficient of analog equalization and the coefficient of digital equalization by estimating frequency characteristics with use of the output signal from the analog/digital converter.