公开(公告)号：US20140269778A1

公开(公告)日：2014-09-18

申请号：US14058718

申请日：2013-10-21

Applicant: Altera Corporation

Inventor： Haiyun Yang ,  David W. Mendel ,  Keith Duwel ,  Huy Ngo ,  Herman Henry Schmit

IPC: H04J3/06

CPC classification number: H04J3/0697 ,  H04J3/0667 ,  H04L1/0042

Abstract: Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.

Abstract translation: 公开了用于允许集成电路或设备内的通信系统中的介质访问控制（MAC）层在例如精确时间协议（PTP）协议时准确地确定时间戳点和时间戳值的系统和方法和系统 正在由通信系统使用。 通信系统可以使用精确时间戳点和时间戳值的这种确定来解释并补偿由MAC层发送的数据帧中的前向纠错（FEC）子层改变的时间偏移。 从FEC向MAC提供反馈，以允许MAC将数据帧的时间戳点和时间戳值对齐前导码精确地确定到由FEC子层输出的FEC比特块的开头。

公开(公告)号：US09300421B2

公开(公告)日：2016-03-29

申请号：US14058718

申请日：2013-10-21

Applicant: Altera Corporation

Inventor： Haiyun Yang ,  David W. Mendel ,  Keith Duwel ,  Huy Ngo ,  Herman Henry Schmit

IPC: H04J3/06

CPC classification number: H04J3/0697 ,  H04J3/0667 ,  H04L1/0042

Abstract: Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.

Abstract translation: 公开了用于允许集成电路或设备内的通信系统中的介质访问控制（MAC）层在例如精确时间协议（PTP）协议时准确地确定时间戳点和时间戳值的系统和方法和系统 正在由通信系统使用。 通信系统可以使用精确时间戳点和时间戳值的这种确定来解释并补偿由MAC层发送的数据帧中的前向纠错（FEC）子层改变的时间偏移。 从FEC向MAC提供反馈，以允许MAC将数据帧的时间戳点和时间戳值对齐前导码精确地确定到由FEC子层输出的FEC比特块的开头。

公开(公告)号：US10374636B1

公开(公告)日：2019-08-06

申请号：US15090170

申请日：2016-04-04

Applicant: ALTERA CORPORATION

Inventor： Haiyun Yang ,  Martin Langhammer ,  Peng Li ,  Divya Vijayaraghavan

IPC: H04L1/00 ,  H03M13/29 ,  H03M13/13

Abstract: One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC encoded at a bus width which is specified within particular constraints. One constraint is that the FEC encoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC encoder bus width. Another constraint may be that the FEC encoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

公开(公告)号：US09331714B1

公开(公告)日：2016-05-03

申请号：US13871227

申请日：2013-04-26

Applicant: ALTERA CORPORATION

Inventor： Haiyun Yang ,  Martin Langhammer ,  Peng Li ,  Divya Vijayaraghavan

IPC: G06F11/00 ,  H03M13/05

CPC classification number: H03M13/05 ,  H03M13/1515 ,  H04L1/20 ,  H04L12/40 ,  H04L12/40013 ,  H04L25/14

Abstract: One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC decoded at a bus width which is specified within particular constraints. One constraint is that the FEC decoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC decoder bus width. Another constraint may be that the FEC decoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及从多通道数据链路接收数据的方法。 数据用具有块长度的FEC码进行编码。 该数据在特定约束条件下指定的总线宽度进行FEC解码。 一个约束是FEC解码器总线宽度（以位为单位）是数据中每个符号数位数的精确倍数。 另一个约束可能是FEC码块长度是FEC解码器总线宽度的精确倍数。 另一个约束可能是FEC解码器总线宽度是多通道接口的多个串行通道的精确倍数。 还公开了其它实施例和特征。

公开(公告)号：US09747076B1

公开(公告)日：2017-08-29

申请号：US14561131

申请日：2014-12-04

Applicant: Altera Corporation

Inventor： Haiyun Yang ,  Tianshu Chi

IPC: G06F7/58

CPC classification number: G06F7/584

Abstract: Integrated circuits with pseudo random bit sequence (PRBS) generation circuitry are provided. The PRBS generation circuitry may be configured to support parallel output generation in multiple modes, where the parallel bit width in each mode can be different. The PRBS generation circuitry may include a linear feedback shift register that implements a desired polynomial, one or more XOR tree circuits that produces the parallel output bits, a multiplexer for selectively routing a subset of the parallel output bits back to the input of the shift register, and a gearbox for performing an adjustable bit width conversion. Configured in this way, the PRBS generation circuitry can provide parallel PRBS generation with an adjustable bit width.

公开(公告)号：US09235540B1

公开(公告)日：2016-01-12

申请号：US13781839

申请日：2013-03-01

Applicant: Altera Corporation

Inventor： Martin Langhammer ,  Haiyun Yang ,  Peng Li

IPC: G06F13/14 ,  G06F13/36 ,  G06F13/40 ,  H03M7/00 ,  H04L27/00

CPC classification number: G06F13/36 ,  G06F13/4022 ,  G06F13/4027 ,  H03M7/00 ,  H03M13/1515 ,  H04L25/14 ,  H04L27/00

Abstract: Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.

Abstract translation: 公开了与发射机接口有关的系统，方法，装置和技术。 软IP发送器接口包括根据多个总线宽度和带宽参数对中的任何一个操作的里德 - 所罗门编码器，以及包括多个齿轮箱的变速箱模块。 多个变速箱以软IP传送器接口指定的总线宽度和时钟速率参数对接收输入数据，并根据物理介质附件（PMA）指定的物理通道数和带宽参数对将输入数据转换为输出数据 ）标准。