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    Methods for built-in self-measurement of jitter for link components
    1.
    发明授权
    Methods for built-in self-measurement of jitter for link components 有权
    用于链路组件的抖动内置自测量方法

    公开(公告)号：US09596160B1

    公开(公告)日：2017-03-14

    申请号：US14529912

    申请日：2014-10-31

    Applicant: ALTERA CORPORATION

    Inventor： Peng Li ,  Masashi Shimanouchi ,  Hsinho Wu

    IPC: H04L12/26

    CPC classification number: H04L43/087 ,  H04L1/205

    Abstract: One embodiment of the present invention relates to a method for built-in self-measurement (BISM) of jitter components. A built-in self-measurement controller on the host integrated circuit (and, in some cases, a slave controller on a partner integrated circuit) may be used to control various switches to form various loopback circuits. A calibrated jittery data pattern is transmitted through each of the various loopback circuits. On-die instrumentation (ODI) circuitry may then be used to measure intrinsic jitter components for each loopback circuit via data representations such as eye-diagrams, or jitter histograms, or bit error ratio bathtub curves. The intrinsic jitter for link components (i.e. the jitter components such as deterministic jitter (DJ), random jitter (RJ), total jitter (TJ)) may then be determined based on the measured intrinsic jitters for the various loopback circuits. Other embodiments and features are also disclosed.

    Abstract translation: 本发明的一个实施例涉及一种用于抖动分量的内置自测量（BISM）的方法。 可以使用主机集成电路（以及在某些情况下，伙伴集成电路上的从控制器）上的内置自测量控制器来控制各种开关以形成各种环回电路。 校准的抖动数据模式通过各个环回电路中的每一个发送。 然后可以使用管芯仪表（ODI）电路来通过数据表示（例如眼图或抖动直方图）或误码率浴缸曲线来测量每个环回电路的固有抖动分量。 然后可以基于所测量的各种环回电路的本征抖动来确定链路组件的固有抖动（即抖动分量，例如确定性抖动（DJ），随机抖动（RJ），总抖动（TJ））。 还公开了其它实施例和特征。

    Techniques For Variable Forward Error Correction
    2.
    发明申请
    Techniques For Variable Forward Error Correction 审中-公开
    可变前向纠错技术

    公开(公告)号：US20160373138A1

    公开(公告)日：2016-12-22

    申请号：US14745870

    申请日：2015-06-22

    Applicant: Altera Corporation

    Inventor： Peng Li ,  Martin Langhammer ,  Jon Long

    IPC: H03M13/35 ,  H04B10/079 ,  H04L1/00

    CPC classification number: H03M13/353 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2906 ,  H04B10/0797 ,  H04L1/0001 ,  H04L1/0009 ,  H04L1/0026 ,  H04L1/004 ,  H04L1/203

    Abstract: A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a second forward error correction code in response to a change in the indication of the line quality of the second data signal.

    Abstract translation: 系统包括编码电路，线路质量监视电路和控制器电路。 编码电路使用第一前向纠错码产生指示编码数据的第一数据信号。 线路质量监视电路使用监视第二数据信号的眼睛监视电路产生第二数据信号的线路质量的指示。 控制器电路使得编码电路响应于第二数据信号的线路质量指示的变化，使用第二前向纠错码来生成第一数据信号中的编码数据。

    System for communications link components
    3.
    发明授权
    System for communications link components 有权

    公开(公告)号：US09369218B1

    公开(公告)日：2016-06-14

    申请号：US14094571

    申请日：2013-12-02

    Applicant: Altera Corporation

    Inventor： Peng Li

    IPC: H04B17/00

    CPC classification number: H04B17/3912

    Abstract: Design systems are provided to assist users in designing circuits that include communications links. A communications link may include a transmitter link subsystem, a receiver link subsystem, and a channel subsystem that interconnects the transmitter and receiver subsystems. A user may specify global link performance characteristics such as bit error rate and data rate. Measured link subsystem performance characteristics may be gathered and stored in a database as probability distribution functions. When analyzing a link, known link subsystems parameters supplied by the user may be used to retrieve appropriate link subsystem performance data. The retrieved link subsystem data and the global link performance data may be analyzed and used to produce recommended subsystem limits. A logic design system may use information on a user's logic design and the recommended limits in producing programmable logic device configuration data.

    Methods for joint optimization of link equalization
    4.
    发明授权
    Methods for joint optimization of link equalization 有权
    链路均衡联合优化的方法

    公开(公告)号：US09237044B1

    公开(公告)日：2016-01-12

    申请号：US13896518

    申请日：2013-05-17

    Applicant: ALTERA CORPORATION

    Inventor： Hsinho Wu ,  Masashi Shimanouchi ,  Peng Li

    IPC: H03H7/30 ,  H03K5/159 ,  H04L25/03

    CPC classification number: H04L25/03343 ,  H04L25/03019 ,  H04L2025/03471 ,  H04L2025/03636 ,  H04L2025/03802

    Abstract: One embodiment relates to a computer-implemented method that selects one of at least three procedures to determine equalization settings jointly for a transmitter and a receiver. A first process may be used if the end-of-channel signal-to-noise ratio (SNR) is greater than an SNR threshold and the equalization capability of the transmitter is greater than the equalization capability of the receiver. A second process may be used if the end-of-channel SNR is greater than the SNR threshold and the equalization capability of the transmitter is less than the equalization capability of the receiver. A third process may be used if the end-of-channel SNR is less than the SNR threshold. Other embodiments and features are also disclosed.

    Abstract translation: 一个实施例涉及一种计算机实现的方法，其选择为发射机和接收机联合确定均衡设置的至少三个过程之一。 如果信道信道信噪比（SNR）大于SNR阈值并且发射机的均衡能力大于接收机的均衡能力，则可以使用第一过程。 如果信道信道SNR大于SNR阈值并且发射机的均衡能力小于接收机的均衡能力，则可以使用第二过程。 如果信道信道的SNR小于SNR阈值，则可以使用第三过程。 还公开了其它实施例和特征。

    Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection system
    8.
    发明授权
    Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection system 有权
    灵活的高速前向纠错（FEC）物理介质连接（PMA）和物理编码子层（PCS）连接系统

    公开(公告)号：US09235540B1

    公开(公告)日：2016-01-12

    申请号：US13781839

    申请日：2013-03-01

    Applicant: Altera Corporation

    Inventor： Martin Langhammer ,  Haiyun Yang ,  Peng Li

    IPC: G06F13/14 ,  G06F13/36 ,  G06F13/40 ,  H03M7/00 ,  H04L27/00

    CPC classification number: G06F13/36 ,  G06F13/4022 ,  G06F13/4027 ,  H03M7/00 ,  H03M13/1515 ,  H04L25/14 ,  H04L27/00

    Abstract: Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.

    Abstract translation: 公开了与发射机接口有关的系统，方法，装置和技术。 软IP发送器接口包括根据多个总线宽度和带宽参数对中的任何一个操作的里德 - 所罗门编码器，以及包括多个齿轮箱的变速箱模块。 多个变速箱以软IP传送器接口指定的总线宽度和时钟速率参数对接收输入数据，并根据物理介质附件（PMA）指定的物理通道数和带宽参数对将输入数据转换为输出数据 ）标准。

    Methods and apparatus for accurate transmitter simulation for link optimization
    9.
    发明授权
    Methods and apparatus for accurate transmitter simulation for link optimization 有权
    用于链路优化的精确发射机仿真的方法和装置

    公开(公告)号：US09178542B1

    公开(公告)日：2015-11-03

    申请号：US14548606

    申请日：2014-11-20

    Applicant: ALTERA CORPORATION

    Inventor： Masashi Shimanouchi ,  Peng Li ,  Hsinho Wu

    IPC: H04L25/49 ,  H04B1/04 ,  H04L25/03

    CPC classification number: H04B1/0475 ,  H03F1/3241 ,  H04B2001/0425 ,  H04L25/03012 ,  H04L25/03343

    Abstract: One embodiment relates to an apparatus for generating a data output signal. The apparatus includes a pre-emphasis filter and an edge-shape filter. The edge-shape filter includes a non-linearity correction stage that applies a non-linearity correction and a linear filter that applies linear filtering. Another embodiment relates to a method of generating tap coefficients for a pre-emphasis filter. A summation of products of tap coefficients and time-shifted base single-bit response waveforms is used to form a first waveform, and a measured single-bit response waveform is used to provide a second waveform. The tap coefficients are adjusted to fit the first waveform to the second waveform. Other embodiments, aspects, and features are also disclosed.

    Abstract translation: 一个实施例涉及用于产生数据输出信号的装置。 该装置包括预加重滤波器和边缘形滤波器。 边缘形状滤波器包括应用非线性校正的非线性校正级和应用线性滤波的线性滤波器。 另一实施例涉及一种为预加重滤波器生成抽头系数的方法。 使用抽头系数和时移基本单位响应波形的乘积的和来形成第一波形，并且使用测量的单位响应波形来提供第二波形。 抽头系数被调整以将第一波形适合于第二波形。 还公开了其它实施例，方面和特征。

    Apparatus and methods for on-die instrumentation
    10.
    发明授权
    Apparatus and methods for on-die instrumentation 有权
    仪器和仪器的设备和方法

    公开(公告)号：US08837571B1

    公开(公告)日：2014-09-16

    申请号：US13958395

    申请日：2013-08-02

    Applicant: Altera Corporation

    Inventor： Yanjing Ke ,  Thungoc M Tran ,  Weiqi Ding ,  Jie Shen ,  Xiong Liu ,  Sangeeta Raman ,  Peng Li

    IPC: H03K5/159 ,  H04L27/01

    CPC classification number: H04L25/03057 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L2025/03356

    Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

    Abstract translation: 一个实施例涉及具有判决反馈均衡和在线仪器的接收机。 时钟数据恢复循环从输入信号获得恢复的时钟信号，并且由恢复的时钟信号触发的第一采样器从输入信号产生恢复的数据信号。 相位内插器接收恢复的时钟信号并产生相位插值时钟信号。 第二取样器由判定反馈均衡模式中的恢复的时钟信号和在片上仪器模式下的相位插值时钟信号触发。 还公开了其它实施例和特征。

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